Wire type assignment for FPGA routing

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 61-67

  Lee, Seokjin ^a   Xiang, Hua ^b   Wong, D F ^b   Sun, Richard Y ^c  

^a The University of Texas at Austin   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c XILINX INC   (United States)

Author keywords

FPGA routing; Min cost flow algorithm; Wire type assignment

Indexed keywords

ALGORITHMS; CALCULATIONS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC DESIGN; OPTIMIZATION;

NETWORK FLOW COMPUTATION; ROUTING CHANNELS; WIRE TYPE ASSIGNMENT ALGORITHM;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0037673253     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611817.611828     Document Type: Conference Paper

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