FPGA global routing based on a new congestion metric

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1995, Pages 372-378

  Chang, Yao Wen ^a   Wong, D F ^a   Wong, C K ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; GRAPH THEORY; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; SWITCHING NETWORKS;

CHANNEL DENSITY; CONGESTION-CONTROL METRIC; FIELD-PROGRAMMABLE GATE ARRAYS; GLOBAL ROUTING; GRAPH MODELING; ROUTING CAPACITY; RUN TIMES; SWITCHED-BLOCK CAPACITY;

LOGIC CIRCUITS;

EID: 0029500697     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)