Timing-driven routing for FPGAs based on Lagrangian relaxation

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2002, Pages 176-181

  Lee, Seokjin ^a   Wong, D F ^a  

^a The University of Texas at Austin   (United States)

Author keywords

FPGA; Lagrangian relaxation; Timing driven routing

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; LAGRANGE MULTIPLIERS; ROUTERS; TIMING CIRCUITS;

LAGRANGIAN RELAXATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036376010     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505388.505431     Document Type: Conference Paper

References (17)

1. A detailed router for field-programmable gate arrays
2. On a new timing-driven tree problem
3. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
4. The transient response of damped linear network with particular regard to wideband amplifiers
5. Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
6. Timing analysis of computer hardware
7. A fast routability-driven router for FPGAs
8. A performance and routability driven router for FPGA's considering path delay
9. PathFinder: A negotiation-based performance-driven router for FPGAs
10. VPR: A new packing, placement and routing tool for FPGA research
11. Graph based analysis of FPGA routing
12. Timing-driven routing for symmetrical-array-based FPGAs