Current mirror test structures for studying adjacent layout effects on systematic transistor mismatch

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2003, Pages 221-226

  Tuinhout, H P ^a   Bretveld, A ^b   Peters, W C M ^c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b Innovation Laboratory   (Netherlands)

^c NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC LOADS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; RESISTORS;

CURRENT MIRRORS;

MOSFET DEVICES;

EID: 0037627996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. H.P. Tuinhout. "Design of Matching Test Structures" ICMTS94 Proceedings of the IEEE International Conference on Microelectronic Test Structures, pp. 21-27, March 1994.
2. H.P. Tuinhout and W.C.M. Peters, "Measurement of lithographical proximity effects on matching of bipolar transistors" ICMTS98 Proceedings of the IEEE International Conference on Microelectronic Test Structures, pp. 7-12, March 1998.
3. P.R.Gray and R.G. Meyer. "Analysis and Design of Analog Integrated Circuits, 2nd ed.", Chapter 4: Transistor current sources and active loads pp. 233-300, John Wiley & Sons, 1984.
4. R.W. Gregor, "On the Relationship Between Topography and Transistor Matching in Analog CMOS Technology", IEEE Transactions on Electron Devices Vol. 39, No. 2, pp. 275-282, February 1992.
5. S. Hausser, S. Majoni, H. Schligtenhorst and G. Kolwe, "Systematic Mismatch in Diffusion Resistors caused by Photolithography", ICMTS02, Proceedings of the IEEE International Conference on Microelectronic Test Structures, pp. 247-250, April 2002.
6. A. Hastings, "The Art of Analog Layout", Several chapters of this book provide useful hints and suggestions concerning mismatch related tricks for analogue circuit layout. Prentice Hall 2001.
7. A. Pergoot, P. Cox, P. Vercruysse, I. Wuyts and P. Raes. "New Method for Monitoring of Analogue Process - Evaluation of the Impact of Metalisation on the Performance of Precise Analogue Resistors " ICMTS98 Proceedings of the IEEE International Conference on Microelectronic Test Structures, pp. 13-17, March 1998.
8. H.P. Tuinhout and M. Vertragt, "Characterization of Systematic MOSFET Current Factor Mismatch Caused by Metal CMP Dummy Structures", IEEE Transactions on Semiconductor Manufacturing, Vol. 14 No. 4, pp. 302-310, November 2001.