A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 76-77

  Farjad Rad, Ramin ^a   Dally, William ^a   Ng, Hoik Tiaq ^a   Poulton, John ^a   Stone, Teva ^a   Rathi, Rohit ^a   Lee, Edward ^a   Huang, David ^a   Edmondson, John ^a   Senthinathan, Ramesh ^a  

^a Velio Communications Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; PHASE LOCKED LOOPS; TIMING JITTER; VARIABLE FREQUENCY OSCILLATORS;

MULTIPLYING DELAY LOCKED LOOPS (MDLL);

DATA COMMUNICATION SYSTEMS;

EID: 0036105957     PISSN: 01936530     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISSCC.2002.992946     Document Type: Article

References (3)

1. A delay line loop for frequency synthesis of de-skewed clock
2. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers