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Volumn 65, Issue 3, 2003, Pages 285-292

Patterning of W/WNx/poly-Si gate electrode using Cl2/O2 plasmas

Author keywords

Etching; Metal gate; Temperature; Tungsten

Indexed keywords

ELECTRODES; ETCHING; PLASMA APPLICATIONS; TUNGSTEN COMPOUNDS;

EID: 0037364982     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(02)00902-4     Document Type: Article
Times cited : (5)

References (7)
  • 1
    • 0030387118 scopus 로고    scopus 로고
    • Gate oxide scaling limits and projection
    • C. Hu, Gate oxide scaling limits and projection. IEDM Tech. Dig. (1996) 319.
    • (1996) IEDM Tech. Dig. , pp. 319
    • Hu, C.1
  • 4
    • 0031634342 scopus 로고    scopus 로고
    • Highly-reliable, low-resistivity bcc-Ta gate MOS technology using low-damage Xe-plasma sputtering and Si-encapsulated silicidation process
    • K. Ino, T. Ushiki, K. Kawai, I. Ohshima, T. Shinohara, T. Ohmi, Highly-reliable, low-resistivity bcc-Ta gate MOS technology using low-damage Xe-plasma sputtering and Si-encapsulated silicidation process, VLSI Tech. (1998) 186.
    • (1998) VLSI Tech. , pp. 186
    • Ino, K.1    Ushiki, T.2    Kawai, K.3    Ohshima, I.4    Shinohara, T.5    Ohmi, T.6
  • 5
    • 0029703324 scopus 로고    scopus 로고
    • Gate oxide integrity (GOI) of MOS transistors with W/TiN stacked gate
    • D.H. Lee, K.H. Yeom, M.H. Cho, N.S. Kang, T.E. Shim, Gate oxide integrity (GOI) of MOS transistors with W/TiN stacked gate, VLSI Tech. (1996) 208.
    • (1996) VLSI Tech. , pp. 208
    • Lee, D.H.1    Yeom, K.H.2    Cho, M.H.3    Kang, N.S.4    Shim, T.E.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.