Dynamic compact models of cooling mounts for fast board level design

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2003, Pages 255-262

  Farkas, G ^a   Poppe, A ^a,b   Kollar, E ^b   Stehouwer, P ^c  

^a MicReD Ltd   (Hungary)

^b BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS   (Hungary)

^c Centre for Quantitative Methods   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; COMPUTER SIMULATION; COOLING; ELECTRONICS PACKAGING; HEAT RESISTANCE; HEAT SINKS; HEAT TRANSFER COEFFICIENTS; OPTIMIZATION; SEMICONDUCTOR JUNCTIONS; SURFACE MOUNT TECHNOLOGY; TEMPERATURE DISTRIBUTION; TEMPERATURE MEASUREMENT; ASSEMBLY; CHIP SCALE PACKAGES; ELECTRIC NETWORK TOPOLOGY; ELECTRONIC COOLING; PROFITABILITY; SEMICONDUCTOR DEVICES; SEMICONDUCTOR INSULATOR BOUNDARIES; TEMPERATURE; THERMAL VARIABLES MEASUREMENT;

COOLING MOUNTS; DYNAMIC COMPACT MODELS; FAST BOARD LEVEL DESIGN; THERMAL CAPACITANCE;

PRINTED CIRCUIT DESIGN; SEMICONDUCTOR DEVICE MODELS;

ELECTRICAL RESISTANCE MEASUREMENT; ELECTRONIC PACKAGING THERMAL MANAGEMENTS; NETWORK TOPOLOGY; PREDICTIVE MODELS; SEMICONDUCTOR DEVICE PACKAGING; THERMAL ENGINEERING;

EID: 0037272310     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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