On the performance of compact thermal models of electronic chip packages in conjugate board level simulation

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2003, Pages 313-318

  DeVoe, Jason ^a   Ortega, Alfonso ^a   Berhe, Mulugeta ^b  

^a University of Arizona   (United States)

^b NONE

Author keywords

CFD; Compact thermal models; Conjugate non conjugate environment

Indexed keywords

BOUNDARY CONDITIONS; COMPUTATIONAL FLUID DYNAMICS; ELECTRIC CONDUCTIVITY OF SOLIDS; ELECTRONICS PACKAGING; ERRORS; EVALUATION; PERFORMANCE; PRINTED CIRCUIT BOARDS; TEMPERATURE MEASUREMENT; AIR; CHIP SCALE PACKAGES; FLUID DYNAMICS; HEAT TRANSFER; PRINTED CIRCUITS; TEMPERATURE; TESTING; THERMAL CONDUCTIVITY; THERMAL VARIABLES MEASUREMENT; THERMOGRAPHY (TEMPERATURE MEASUREMENT);

COMPACT THERMAL MODELS; COMPUTATIONAL HEAT TRANSFER; CONJUGATE BOARD LEVEL SIMULATION; FULLY DETAILED MODEL; SOFTWARE PACKAGE ICEPAK;

SEMICONDUCTOR DEVICE MODELS; PRINTED CIRCUIT BOARDS;

AEROSPACE SIMULATION; BOARD-LEVEL SIMULATIONS; COMPACT THERMAL MODELS; ELECTRONIC PACKAGING THERMAL MANAGEMENTS; JUNCTION TEMPERATURES; SOLID MODEL; SOLUTION METHODOLOGY; THREE ORDERS OF MAGNITUDE;

EID: 0037272227     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

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