Design techniques for EEPROMs embedded in portable systems on chips

IEEE Design and Test of Computers

Volumn 20, Issue 1, 2003, Pages 68-75

  Daga, Jean Michel ^b   Papaix, Caroline ^a   Merandat, Marc ^b   Ricard, Stephane ^b   Medulla, Giuseppe ^b   Guichaoua, Jeanine ^b   Auvergne, Daniel ^b  

^a Design Technology Department   (France)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION;

BATTERY-POWERED DEVICES;

PROM;

EID: 0037246493     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1173055     Document Type: Article

References (12)

1. N. Otsuka and M.A. Horowitz, "Circuit Techniques for 1.5-V Power Supply Memory," IEEE J. Solid-State Circuits, vol. 32, no. 8, Aug. 1997, pp. 1217-1230.
2. T. Tanzawa et al., "Circuit Technologies for a Single-1.8V Flash Memory," Proc. 1997 Symp. VLSI Circuits, Digest of Technical Papers, IEEE Press, Piscataway, N.J., 1997, pp. 63-64.
3. T. Tanzawa and T. Tanaka, "A Dynamic Analysis of the Dickson Charge Pump Circuit," IEEE J. Solid-State Circuits, vol. 32, no. 8, Aug. 1997, pp. 1231-1240.
4. J.-T. Wu and K.-L. Chang, "MOS Charge Pumps for Low-Voltage Operation," IEEE J. Solid-State Circuits, vol. 33, no. 4, Apr. 1998, pp. 592-597.
5. K.-H. Choi et al., "Floating-Well Charge Pump Circuits for Sub-2.0V Single Supply Flash Memories," Proc. 1997 Symp. VLSI Circuits, Digest of Technical Papers, IEEE Press, Piscataway, N.J., 1997, pp. 61-62.
6. J.F. Dickson, "On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique," IEEE J. Solid-State Circuits, vol. 11, no. 3, June 1976, pp. 374-378.
7. T. Tanzawa and T. Tanaka, "A Stable Programming Pulse Generator for Single Power Supply Flash Memories," IEEE J. Solid-State Circuits, vol. 32, no. 6, June 1997, pp. 845-851.
8. H. Oguey and D. Aebischer, "CMOS Current Reference Without Resistance," IEEE J. Solid-State Circuits, vol. 32, no. 7, July 1997, pp. 1132-1135.
9. T. Tanzawa and S. Atsumi, "Optimization of Word Line Booster Circuits for Low-Voltage Flash Memories," IEEE J. Solid-State Circuits, vol. 34, no. 8, Aug. 1999, pp. 1091-1098.
10. A. Cataldo, "Flash Device Reads, Writes at 1.8V," EE Times, Mar. 2000; http://www.eetimes.com/news/97/985news/flash.html.
11. J.C. Chen et al., "A 2.7V Only 8Mb×16 NOR Flash Memory," Proc. 1996 Symp. VLSI Circuits, Digest of Technical Papers IEEE Press, Piscataway, N.J., 1996, pp. 172-173.
12. S. Atsumi et al., "A Channel-Erasing 1.8V-Only 32-Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme," IEEE J. Solid-State Circuits, vol. 35, no. 11, Nov. 2000, pp. 1648-1654.