Differential CMOS edge-triggered flip-flop based on clock racing

Electronics Letters

Volumn 36, Issue 12, 2000, Pages 1012-1013

  Moisiadis, Y ^a   Bouras, I ^a,b  

^a INSTITUTE OF MICROELECTRONICS   (Greece)

^b UNIVERSITY OF ATHENS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; ELECTRIC LOSSES; ELECTRIC POTENTIAL; TIMING CIRCUITS;

EDGE-TRIGGERED FLIP FLOPS;

FLIP FLOP CIRCUITS;

EID: 0033690424     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000752     Document Type: Article

References (4)

1. WU, X., and WEI, J.: 'CMOS edge-triggered flip-flop using one latch', Electron. Lett., 1998, 34, (16), pp. 1581-1582
2. YUAN, J., and SVENSSON, C.: 'New single-clock CMOS latches and flip-flops with improved speed and power savings', IEEE J. Solid-State Circuits, 1997, 32, (1), pp. 62-69
3. KO, U., HILL, A., and BALSARA, P.T.: 'Design techniques for high performance, energy-efficient control logic'. ISLPED Dig. Tech. Papers, August 1996
4. STOJANOVIC, V., and OKLOBDZIJA, V.G.: 'Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems', IEEE J. Solid-State Circuits, 1999, 34, (4), pp. 536-548