A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 6, 2002, Pages 913-918

  Chung, Wai ^a   Lo, Timothy ^a   Sachdev, Manoj ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Digital CMOS; Flip flop; Low power; Low voltage; VLSI

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ENERGY DISSIPATION; ENERGY UTILIZATION;

EDGE-TRIGGERED FLIP-FLOPS;

FLIP FLOP CIRCUITS;

EID: 0037002150     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.808429     Document Type: Article

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