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Volumn 2, Issue , 2002, Pages 1045-1050

Low-temperature micromachined cMUTs with fully-integrated analogue front-end electronics

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; MICROMACHINING; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING SILICON; SIGNAL TO NOISE RATIO; SILICON NITRIDE; SUBSTRATES;

EID: 0036989220     PISSN: 10510117     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (39)

References (6)
  • 1
    • 0035731025 scopus 로고    scopus 로고
    • A cost-effective & manufacturable route to the fabrication of high-density 2D cMUT arrays & signal conditioning electronics on the same silicon substrate
    • R.A. Noble et al, "A cost-effective & manufacturable route to the fabrication of high-density 2D cMUT arrays & signal conditioning electronics on the same silicon substrate", Proc. IEEE, Ultras. Sym, Vol. 2, pp. 941-944, 2001.
    • (2001) Proc. IEEE, Ultras. Sym , vol.2 , pp. 941-944
    • Noble, R.A.1
  • 2
    • 0034579981 scopus 로고    scopus 로고
    • An efficient electrical addressing method using through-wafer vias for 2D ultrasonic arrays
    • C.H. Cheng, E.H. Chow, X. Jin, S. Ergun, B.T. Khuri-Yakub, "An efficient electrical addressing method using through-wafer vias for 2D ultrasonic arrays", Proc. IEEE, Ultras. Sym, Vol. 2, pp. 1179-1182, 2000.
    • (2000) Proc. IEEE, Ultras. Sym , vol.2 , pp. 1179-1182
    • Cheng, C.H.1    Chow, E.H.2    Jin, X.3    Ergun, S.4    Khuri-Yakub, B.T.5
  • 4
    • 0035498415 scopus 로고    scopus 로고
    • Novel, wide bandwidth micromachined ultrasonic transducers
    • Nov.
    • R.A.Noble et al "Novel, Wide Bandwidth Micromachined Ultrasonic Transducers", IEEE Trans Ultras. Ferr. Freq Cont., pp. 1495-1507, Nov. 2001.
    • (2001) IEEE Trans Ultras. Ferr. Freq Cont. , pp. 1495-1507
    • Noble, R.A.1
  • 6
    • 0035763547 scopus 로고    scopus 로고
    • Engineering in- and out-of-plane stress in PECVD silicon nitride for CMOS-compatible surface micromachining
    • Oct.
    • R.R.Davies et al, "Engineering In- and Out-of-Plane Stress in PECVD Silicon Nitride for CMOS-Compatible Surface Micromachining", SPIE Micromachining and Microfabrication, Vol 4557, pp.320-328, Oct. 2001.
    • (2001) SPIE Micromachining and Microfabrication , vol.4557 , pp. 320-328
    • Davies, R.R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.