A high-performance encoder with priority lookahead

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 47, Issue 9, 2000, Pages 1390-1393

  Delgado Frias, Joseé G ^a   Nyathi, Jabulani ^b  

^a University of Virginia   (United States)

^b State University of New York   (United States)

Author keywords

Complementary metal oxide semiconductor (cmos) encoder; Dynamic circuits; High speed circuits; Lookahead scheme; Priority chain encoder

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; TRANSISTORS; VLSI CIRCUITS;

PRIORITY ENCODERS; PRIORITY LOOKAHEAD;

ENCODING (SYMBOLS);

EID: 0034262694     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.883335     Document Type: Article

References (8)

1. E.D. Adamides, P. Lliades, I. Argyrakis, P. Tsalides, and A. Thanailakis, Cellular logic bus arbitration, IEE Proc. Part E, Comput. Dig. Tech., vol. 140, no. 6, pp. 289-296, Nov. 1993.
2. A. Khu, Integrated PLD's support multibus II bus arbitration, EDN, vol. 33, pp. 165-170, Jan. 7, 1988.
3. J.L. Hennessy and D.A. Patterson, Computer Architecture - A Quantitative Approach, 2nd ed. New York: Morgan Kaufmann, 1994.
4. P.H. Garrett, Advanced Instrumentation and Computer I/O Design - Real-Time System Computer Interface Engineering. Piscataway, NJ: IEEE Press, 1994.
5. S. Murugesan, Use priority encoders for fast data comparison, Electron. Eng., vol. 42, p. 24, July 1989.
6. J.G. Delgado-Frias, J. Nyathi, and D.H. Summerville, A programmable dynamic interconnection network router with hidden refresh, IEEE Trans. Circuits and Syst. I, vol. 45, pp. 1182-1190, Nov. 1998.
7. J.B. Kuo, H.J. Liao, and H.P. Chen, A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit, IEEE J. Solid-State Circuits, vol. 28, pp. 375-378, Mar. 1993.
8. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.