-
1
-
-
0022769976
-
-
677-691, Aug. 1986.
-
R.E. Bryant, "Graph based algorithms for boolean function manipulation," IEEE Trans. Comput., vol. C-35, pp. 677-691, Aug. 1986.
-
Graph Based Algorithms for Boolean Function Manipulation, IEEE Trans. Comput., Vol. C-35, Pp.
-
-
Bryant, R.E.1
-
3
-
-
0026981959
-
-
29th ACM/IEEE Design Automation Conf., 1992, pp. 543-548.
-
S. Chen, H. Chen, and D. Du, "The role of long and short paths in circuit performance optimization," in Proc. 29th ACM/IEEE Design Automation Conf., 1992, pp. 543-548.
-
H. Chen, and D. Du, the Role of long and Short Paths in Circuit Performance Optimization, in Proc.
-
-
Chen, S.1
-
5
-
-
0026981958
-
-
29th Design Automation Conf., June 1992, pp. 549-555.
-
S. Devadas, K. Keutzer, and S. Malik, "Certified timing verification and transition delay of a logic circuit," in Proc. 29th Design Automation Conf., June 1992, pp. 549-555.
-
K. Keutzer, and S. Malik, Certified Timing Verification and Transition Delay of a Logic Circuit, in Proc.
-
-
Devadas, S.1
-
7
-
-
33747769230
-
-
1987.
-
B. Ekroot, "Optimization of pipelined processors by insertion of combinational logic delay," Ph.D. thesis, Stanford Univ., Stanford, CA, 1987.
-
Optimization of Pipelined Processors by Insertion of Combinational Logic Delay, Ph.D. Thesis, Stanford Univ., Stanford, CA
-
-
Ekroot, B.1
-
8
-
-
0025464163
-
-
39, pp. 945-951, July 1990.
-
J. Fishburn, "Clock skew optimization," IEEE Trans. Comput., vol. 39, pp. 945-951, July 1990.
-
Clock Skew Optimization, IEEE Trans. Comput., Vol.
-
-
Fishburn, J.1
-
9
-
-
0028484138
-
-
13. pp. 987-1004, Aug. 1994.
-
C.T. Gray, W. Liu, and R.K. Cavin III, "Timing constraints for wavepipelined systems," IEEE Trans. Computer-Aided Design, vol. 13. pp. 987-1004, Aug. 1994.
-
W. Liu, and R.K. Cavin III, Timing Constraints for Wavepipelined Systems, IEEE Trans. Computer-Aided Design, Vol.
-
-
Gray, C.T.1
-
11
-
-
0027061382
-
-
1991, pp. 216-221.
-
S. Huang, T. Parng, and J. Shyu, "A new approach to solving false path problem in timing analysis," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1991, pp. 216-221.
-
T. Parng, and J. Shyu, a New Approach to Solving False Path Problem in Timing Analysis, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov.
-
-
Huang, S.1
-
16
-
-
33747783202
-
-
1992.
-
W. Lam, R. Brayton, and A. Sangiovanni-Vincentelli, "Exact minimum delay computations and clock frequencies," Univ. California, Berkeley, ERL Memo, UCB/ERL, 1992.
-
R. Brayton, and A. Sangiovanni-Vincentelli, Exact Minimum Delay Computations and Clock Frequencies, Univ. California, Berkeley, ERL Memo, UCB/ERL
-
-
Lam, W.1
-
17
-
-
33747789522
-
-
1992.
-
"Minimum cycle time of synchronous circuit with bounded delays," Univ. California, Berkeley, ERL Memo, UCB/ERL M92/56, May 1992.
-
Of Synchronous Circuit with Bounded Delays, Univ. California, Berkeley, ERL Memo, UCB/ERL M92/56, May
-
-
Time, C.1
-
22
-
-
0027062433
-
-
1991, pp. 312-315.
-
L. Liu.H. Chen, and D. Du, "The calculation of signal stable ranges in combinational circuits," in Proc. IEEF. Int. Conf. Cnmputer-Aided Design, 1991, pp. 312-315.
-
Chen, and D. Du, the Calculation of Signal Stable Ranges in Combinational Circuits, in Proc. IEEF. Int. Conf. Cnmputer-Aided Design
-
-
Liu.h, L.1
-
23
-
-
84931689614
-
-
628-639, Aug. 1966.
-
H. Loomis, "The maximum rate accumulator," IEEE Trans. Electron. Comput., vol. EC-15, pp. 628-639, Aug. 1966.
-
The Maximum Rate Accumulator, IEEE Trans. Electron. Comput., Vol. EC-15, Pp.
-
-
Loomis, H.1
-
25
-
-
33747789521
-
-
1990.
-
K. Sakallah, T. Mudge, T. Burks, and E. Davidson, "Synchronization of pipelines," Computer Science and Engineering, Univ. Michigan, Ann Arbor, Tech. Rep. CSE-TR-97-91, Feb. 1990.
-
T. Mudge, T. Burks, and E. Davidson, Synchronization of Pipelines, Computer Science and Engineering, Univ. Michigan, Ann Arbor, Tech. Rep. CSE-TR-97-91, Feb.
-
-
Sakallah, K.1
-
27
-
-
0024878790
-
-
1989, pp. 270 273.
-
D. Wong, D. DeMicheli, and G. Flynn, "Inserting active delay elements to achieve wave pipelining," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1989, pp. 270 273.
-
D. DeMicheli, and G. Flynn, Inserting Active Delay Elements to Achieve Wave Pipelining, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov.
-
-
Wong, D.1
-
28
-
-
0026869432
-
-
2.5x normal clock frequency, IEEE J. Solid-State Circuits, vol. 27, pp. 745-753, May 1992.
-
D. Wong.D. DeMicheli, G. Flynn, and R. Huston, "A bipolar population counter using wave pipelining to achieve 2.5x normal clock frequency," IEEE J. Solid-State Circuits, vol. 27, pp. 745-753, May 1992.
-
DeMicheli, G. Flynn, and R. Huston, a Bipolar Population Counter Using Wave Pipelining to Achieve
-
-
Wong.d, D.1
|