An iterative improvement circuit partitioning algorithm under path delay constraints

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E83-A, Issue 12, 2000, Pages 2569-2576

  Ami, Jun'ichiro Min ^a,c   Koide, Tetsushi ^a,b   Wakabayashi, ShiN'ichi ^a,b  

^a HIROSHIMA UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c NTT CORPORATION   (Japan)

Author keywords

Circuit partitioning; Ff>i method; Iterative improvement; Path cut number; Timing constraint

Indexed keywords

CIRCUIT PARTITIONING ALGORITHMS; FIDUCCIA-MATTHEYSES METHOD;

ALGORITHMS; CONSTRAINT THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS;

VLSI CIRCUITS;

EID: 0034506764     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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