Low power design technology for digital lsis

IEICE Transactions on Electronics

Volumn E79-C, Issue 12, 1996, Pages 1639-1648

  Enomoto, Tadayoshi ^a  

^a CHUO UNIVERSITY   (Japan)

Author keywords

Active power dissipation; Caws lsis; Gaas lsis; Low power circuit technology; LSI; Multi media lsis; Power dissipation; Stand by power dissipation; Video codec lsis

Indexed keywords

ADDERS; CALCULATIONS; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; DIGITAL SIGNAL PROCESSING; ENERGY DISSIPATION; LOGIC CIRCUITS; MULTIPLYING CIRCUITS; SEMICONDUCTING GALLIUM ARSENIDE; VIDEO SIGNAL PROCESSING;

LOW POWER CIRCUIT TECHNOLOGY; VIDEO CODECS; VIDEO SIGNAL PARALLEL PIPELINE PROCESSOR;

LSI CIRCUITS;

EID: 0030402854     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (36)

1. B. A. Ackland, The role of VLSI in multimedia, IEEE J. Solid-State Circuits, vol. SC-29, no. 4, pp. 381-388, April 1994.
2. R. Kasai and T. Minami, An overview of video coding VLSIs, IEICE Trans. Electron., vol. E77-C, no. 12, pp. 1920-1929, Dec. 1994.
3. M. Yoshimoto, S. Nakagawa, T. Matsumura, K. Ishihara, and S. Uramoto, ULSI realization of MPEG2 realtime video encoder and decoder An overview, IEICE Trans. Electron., vol. E78-C, no. 12, pp. 1668-1681, Dec. 1995.
4. M. Yamashina, T. Enomoto, T. Kunio, I. Tamitani, H. Harasaki, T. Nishitani, M. Sato, and K. Kikuchi, A realtime microprogrammable video signal LSI, Digest of Technical Papers, ISSCC, THPM 15.3, pp. 184-185, 393, Feb. 1987.
5. T. Enomoto, M. Yamashina, T. Kunio, I. Tamitani, H. Harasaki, Y. Endo, T. Nishitani, M. Satoh, and K. Kikuchi, A microprogrammable realtime video signal processor (VSP) LSI for motion compensation and vector quantization Proc. of Custom Integrated Circuits Conference, pp. 303-306, May 1987.
6. K. Kikuchi, Y. Nukata, Y. Aoki, T. Kanou, Y. Endo, and T. Nishitani, A single-chip 16-bit 25-ns real-time video/ image signal processor, IEEE J. Solid-State Circuits, vol. SC-24, no. 6, pp. 1662-1667, Dec. 1989.
7. S. Nakagawa, H. Terane, T. Matsumura, H. Segawa, M. Yoshimoto, H. Shinohara, H. Ohira, Y. Katoh, M. Iwatsuki, and K. Tabuchi, A 50ns video signal processor, Digest of Technical Papers, ISSCC, pp. 168-169, 328, Feb. 1989.
8. J. Goto, K. Ando, T. Inoue, M. Yamashina, H. Yamada, and T. Enomoto, 250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI, IEEE J. SolidState Circuits, vol. SC-26, no. 12, pp. 1876-1884, Dec. 1991.
9. T. Minami, H. Yamauchi, Y. Tashiro, R. Kasai, J. Takahashi, S. Hamaguchi, K. Endo, and T. Tajiri, A 300MOPS video signal processor with parallel architecture, Digest of Technical Papers, ISSCC, pp. 252-253, 324, Feb. 1991.
10. M. Toyokura, K. Okamoto, H. Kodama, A. Ohtani, T. Araki, and K. Aono, A video digital signal processor with vector-pipeline architecture, Digest of Technical Papers, ISSCC, WP4.6, pp. 72-73, 248, Feb. 1992.
11. T. Inoue, J. Goto, M. Yamashina, K. Suzuki, M. Nomura, Y. Koseki, T. Kimura, T. Atsumo, M. Motomura, B. S. Shih, T. Horiuchi, N. Hamatake, K. Kumagai, T. Enomoto, H. Yamada, and M. Takada, A 300-MHz 16-bit BiCMOS video signal processor, Digest of Technical Papers, ISSCC, WP2.6, pp. 37-38, 258,Veb. 1993.
12. T. Demura, T. Oto, K. Kitagaki, S. Ishiwara, G. Otomo, S. Michinaka, S. Suzuki, N. Goto, M. Matsui, H. Hara, T. Nagamatsu, K. Seta, T. Shimazawa, K. Maeguchi, T. Odaka, Y. Uetani, T. Oku, T. Yamakage, and T. Sakurai, A single-chip MPEG2 video decoder LSI, Digest of Technical Papers, ISSCC, WP 4.4, pp. 72-73, 313, Feb. 1994.
13. M. Toyokura, M. Saishi, S. Kuromaru, K. Yamauchi, H. Imanishi, T. Ougi, A. Watanabe, T. Morishige, H. Kodama, E. Miyagoshi, K. Okamoto, M. Gion, T. Minemura, A. Ohtani, T. Araki, K. Aono, H. Takeno, T. Akiyama, and B. Wilson, A video DSP with a macroblock-level-pipeline and a SIMD type vectorpipeline architecture for MPEG2 codec, Digest of Technical Papers, ISSCC, WP 4.5, pp. 74-75, 314, Feb. 1994.
14. K. Suguri, T. Minami, H. Matsuda, R. Kusaba, T. Kondo, R Kasai, T. Watanabe, H. Satoh, N. Shinbata, Y. Tashiro, T. Izuoka, H. Yamauchi, and H. Kotera, A real-time motion estimation and compensation LSI with widesearch range for MPEG2 video encoding, Digest of Technical Papers, ISSCC, FP15.1, pp. 242-243, 453, Feb. 1996.
15. H. Harrand, M. Henry, P. Chaisemartin, P. Mougeat, Y. Durand, A. Toumier, R. Wilson, J-C. Herluison, J-C. Lonechambon, J-L. Bauer, M. Runtz, and J. Bulone, A sin2fe-chip videophone video encoder/decoder, Digest of Technical Papers, ISSCC, FA 17.4, pp. 292-293, 382, Feb. 1995.
16. D. Brinthaupt, J. Knobloch, J. Othmer, B. Petryna, and M. Uyttendaele, A programmable audio/video processor for H.320, H.324 and NIPEG, Digest of Technical Papers, ISSCC, FA 15.2, pp. 244-245, Feb. 1996.
17. K. Hasegawa, K. Ohara, A. Oka, T. Kamada, Y. Nagaoka, K. Yano, E. Yamauchi, T. Kashio, and T. Nakagawa, Low power video encoder/decoder chip set for digital VCRs, Digest of Technical Papers, ISSCC, FA 10.2, pp. 164-165, 437, Feb. 1996.
18. T. Enomoto, High-throughput technologies for video signal processor (VSP) LSIs, IEICE Trans. Electron., vol. E79-C, no. 4, pp. 459-471, April 1996.
19. S. Horiguchi, T. Tsukahara, and H. Fukuda, Low-power LSI circuit technologies for portable terminal equipment, IEICE Trans. Electronics, vol. E-78C, no. 12, pp. 1655-1667, Dec. 1995.
20. T. Enomoto, Low power circuit technology for multimedia LSIs, Proc. of IEICE of Japan, vol.79, no. 3, pp. 296-306, March 1996.
21. A. Hirobe, H. Iwata, F. Yamane, and T. Enomoto, Technologies for power reduction of GaAs DCFL LSIs, Technical Report of Integrated Circuits and Devices, ICD95-46, pp. 39-46, June 1995.
22. H. Iwata, A. Hirobe, and T. Enomoto, Low power circuit technologies for GaAs DCFL SRAMs, Technical Report of Integrated Circuits and Devices, ICD95-29, pp. 47-54, May 1995.
23. N. H. E. Weste and K. Eshraghiam, Principle of CMOS VLSI Design : A System Perspective, Section 4.4, Addison-Wesley Publishing Co., Readinc, Massachusetts, 1985.
24. M. Takeuchi, A. Hirobe S. Mizuno, and T. Enomoto, Low power technologies for CMOS pipeline multipliers, Proc. of IEICE National Conference, C-556, p. 172, March 1996.
25. N. Hayashi, T. Kitsuki, I. Tamitani, H. Honma, Y. Ooi, T. Miyazaki, and K. Oobuchi, A bidirectional motion compensation LSI with a compact motion estimator, IEICE Trans. Electronics, vol. E-78C, no. 12, pp. 16821690, Dec. 1995.
26. A. Otani, Y. Matsumoto, M. Gion, H. Yoshida, T. Araki, A. Ubukata, M. Serizawa, K. Aoki, A. Sola, A. Nagata, and K. Aono, A motion estimation processor for MPEG2 video real time encoding at wide search range, Proc. CICC, pp. 405-408, May 1995.
27. H-D Lin, A. Anesko, and B Petryna, A 14GOPS programmable motion estimator for H.26x video coding, Digest of Technical Papers, ISSCC, FP15.3, pp. 246-247, 454, Feb. 1996.
28. W. Chen, C. Smith, and S. Fralick, A fast computational algorithm for the discrete cosine transform, IEEE Trans. Commun., vol. COM-25, pp. 1004-1009, Sept. 1977.
29. M-T. Sun, T-C. Chen, and A. M. Gottlieb, VLSI implementation of 16x16 discrete cosine transform, IEEE Trans. Circuits and Systems, vol.36, no. 4, pp. 610-616, April 1989.
30. A. Peled and B. Liu, A new hardware realization of digital filter, IEEE Trans. Acoust., Speech & Signal Process., vol. ASSP-22, no. 6, pp. 456-462, Dec. 1974.
31. T. Kuroda, Pass-transistor circuit technology, Proc. 15th Workshop of Organization of Microelectronics, pp. 17-29, Nov. 1995.
32. M. Matsui, H. Hara, K. Seta, Y. Uetani, L-S. Kim, T. Nagamatsu, T. Shimazawa, S. Mita, G. Otomo, T. Oto, Y. Watanabe, F. Sano, A. Chiba, K. Matsuda, and T. Sakurai, 200-MHz video compression macrocells using lowswing differential logic, Digest of Technical Papers, ISSCC, WP 4.6, pp. 76-77, 314, Feb. 1994.
33. S. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, Y. Yamashita, H. Terane, and M. Yoshimoto, A 100-MHz 2-D discrete cosine transform core processor. IEEE J. Solid-State Circuits, vol. SC-27, no. 4, pp. 492-499, April 1992.
34. S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, and J. Yamada, A IV multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application, Digest of Technical Papers, ISSCC, FA 10.4, pp. 168-169, 438, Feb. 1996.
35. A. Hirobe and T. Enomoto, Stand-by power elimination for GaAs DCFL circuits, Proc. of IEICE National Conference, C-499, p. 115, March 1996.
36. T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, A 0.9 V 150 MHz 10 mW 4 mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme, Digest of Technical Papers, ISSCC, FA 10.3, pp. 166:167, 437, Feb. 1996.