Iterative remapping for logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 10, 1998, Pages 948-964

  Benini, Luca ^a,b,c   Vuillod, Patrick ^a,b   De Micheli, Giovanni ^a,c  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b STANFORD UNIVERSITY   (United States)

^c Synopsys EPIC Tools Group   (France)

Author keywords

Boolean algebra; Circuit optimization; Circuit synthesis; Logic design

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC CIRCUITS; OPTIMIZATION;

ITERATIVE REMAPPING;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032182698     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.728916     Document Type: Article

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