-
1
-
-
0017983865
-
Binary decision diagrams
-
S. B. Akers, “Binary decision diagrams,” IEEE Trans. Comput., vol. C-27, pp. 509-516, 1978.
-
(1978)
IEEE Trans. Comput
, vol.27
, pp. 509-516
-
-
Akers, S.B.1
-
3
-
-
0025558645
-
Efficient implementation of a BDD package
-
June
-
K. S. Brace, R. L. Rudell, and R. E. Bryant, “Efficient implementation of a BDD package,” in Proc. Design Automation Conf., June 1990, pp. 40-45.
-
(1990)
Proc. Design Automation Conf
, pp. 40-45
-
-
Brace, K.S.1
Rudell, R.L.2
Bryant, R.E.3
-
4
-
-
0018456690
-
New methods to color vertices of a graph
-
D. Brélaz, “New methods to color vertices of a graph,” Commun. ACM, vol. 22, pp. 251-256, 1979.
-
(1979)
Commun. ACM
, vol.22
, pp. 251-256
-
-
Brélaz, D.1
-
5
-
-
0022769976
-
Graph-based algorithms for Boolean function manipulation
-
Aug
-
R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,” IEEE Trans. Comput., vol. C-35, pp. 677-691, Aug. 1986.
-
(1986)
IEEE Trans. Comput
, vol.35
, pp. 677-691
-
-
Bryant, R.E.1
-
6
-
-
0026913667
-
Symbolic Boolean manipulation with ordered binary decision diagrams
-
R. E. Bryant, “Symbolic Boolean manipulation with ordered binary decision diagrams,” ACM, Comp. Surveys, vol. 24, pp. 293-318, 1992.
-
(1992)
ACM, Comp. Surveys
, vol.24
, pp. 293-318
-
-
Bryant, R.E.1
-
7
-
-
0031340523
-
Logic synthesis for large pass transistor circuits
-
Nov
-
P. Buch, A. Narayan, A. R. Newton, and A. L. Sangiovanni-Vincentelli, “Logic synthesis for large pass transistor circuits,” in Proc. Int. Conf. CAD, Nov. 1997, pp. 663-670.
-
(1997)
Proc. Int. Conf. CAD
, pp. 663-670
-
-
Buch, P.1
Narayan, A.2
Newton, A.R.3
Sangiovanni-Vincentelli, A.L.4
-
8
-
-
0027969451
-
Minimizing ROBDD size of incompletely specified multiple output functions
-
Mar
-
S. Chang, D. Cheng, and M. Marek-Sadowska, “Minimizing ROBDD size of incompletely specified multiple output functions,” in Proc. European Design & Test Conf., Mar. 1994, pp. 620-624.
-
(1994)
Proc. European Design & Test Conf
, pp. 620-624
-
-
Chang, S.1
Cheng, D.2
Marek-Sadowska, M.3
-
10
-
-
84856140605
-
Verification of sequential machines based on symbolic execution
-
O. Coudert, C. Berthet, and J. C. Madre, “Verification of sequential machines based on symbolic execution,” in Proc. Automatic Verification Methods for Finite State Systems, LNCS 407, 1989, pp. 365-373.
-
(1989)
Proc. Automatic Verification Methods for Finite State Systems, LNCS
, vol.407
, pp. 365-373
-
-
Coudert, O.1
Berthet, C.2
Madre, J.C.3
-
11
-
-
0002684652
-
Verification of sequential machines using Boolean functional vectors
-
O. Coudert, C. Berthet, and J. C. Madre, “Verification of sequential machines using Boolean functional vectors,” in Proc. IFIP Int. Workshop on Applied Formal Methods for Correct VLSI Design, 1989, pp. 111-128.
-
(1989)
Proc. IFIP Int. Workshop on Applied Formal Methods for Correct VLSI Design
, pp. 111-128
-
-
Coudert, O.1
Berthet, C.2
Madre, J.C.3
-
12
-
-
0011769081
-
Identification of symmetry, redundancy and equivalence of Boolean functions
-
D. L. Dietmeyer and P. R. Schneider, “Identification of symmetry, redundancy and equivalence of Boolean functions,” IEEE Trans. Electron. Comput., vol. EC-16, pp. 804-817, 1967.
-
(1967)
IEEE Trans. Electron. Comput
, vol.16
, pp. 804-817
-
-
Dietmeyer, D.L.1
Schneider, P.R.2
-
13
-
-
85013939530
-
Sympathy: Fast exact minimization of fixed polarity reed-muller expressions for symmetric functions
-
Mar
-
R. Drechsler and B. Becker, “Sympathy: Fast exact minimization of fixed polarity reed-muller expressions for symmetric functions,” in Proc. European Design & Test Conf., Mar. 1995, pp. 91-97.
-
(1995)
Proc. European Design & Test Conf
, pp. 91-97
-
-
Drechsler, R.1
Becker, B.2
-
16
-
-
0018038632
-
A digital synthesis procedure under function symmetries and mapping methods
-
C. R. Edwards and S. L. Hurst, “A digital synthesis procedure under function symmetries and mapping methods,” IEEE Trans. Comput., vol. C-27, pp. 985-997, 1978.
-
(1978)
IEEE Trans. Comput
, vol.27
, pp. 985-997
-
-
Edwards, C.R.1
Hurst, S.L.2
-
17
-
-
0027810291
-
Dynamic variable reordering for BDD minimization
-
Sept
-
E. Felt, G. York, R. Brayton, and A. Sangiovanni-Vincentelli, “Dynamic variable reordering for BDD minimization,” in Proc. European Design Automation Conf., Sept. 1993, pp. 130-135.
-
(1993)
Proc. European Design Automation Conf
, pp. 130-135
-
-
Felt, E.1
York, G.2
Brayton, R.3
Sangiovanni-Vincentelli, A.4
-
18
-
-
0032311880
-
Symbolic Algorithms for layout-oriented synthesis of pass transistor logic circuits
-
Nov
-
F. Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, and F. Somenzi, “Symbolic Algorithms for layout-oriented synthesis of pass transistor logic circuits,” in Proc. Int. Conf. CAD, Nov. 1998, pp. 235-241.
-
(1998)
Proc. Int. Conf. CAD
, pp. 235-241
-
-
Ferrandi, F.1
Macii, A.2
Macii, E.3
Poncino, M.4
Scarsi, R.5
Somenzi, F.6
-
19
-
-
0027800929
-
Interleaving based variable ordering methods for ordered binary decision diagrams
-
CAD, Nov
-
H. Fujii, G. Ootomo, and C. Hori, “Interleaving based variable ordering methods for ordered binary decision diagrams,” in Proc. Int. Conf. CAD, Nov. 1993, pp. 38-41.
-
(1993)
Proc. Int. Conf
, pp. 38-41
-
-
Fujii, H.1
Ootomo, G.2
Hori, C.3
-
20
-
-
0024173411
-
Evaluation and improvements of Boolean comparison method based on binary decision diagrams
-
CAD, Nov
-
M. Fujita, H. Fujisawa, and N. Kawato, “Evaluation and improvements of Boolean comparison method based on binary decision diagrams,” in Proc. Int. Conf. CAD, Nov. 1988, pp. 2-5.
-
(1988)
In Proc. Int. Conf
, pp. 2-5
-
-
Fujita, M.1
Fujisawa, H.2
Kawato, N.3
-
21
-
-
0027047925
-
On variable ordering of binary decision diagrams for the application of multi-level synthesis
-
Design Automation, Feb
-
M. Fujita, Y. Matsunaga, and T. Kakuda, “On variable ordering of binary decision diagrams for the application of multi-level synthesis,” in Proc. European Conf. Design Automation, Feb. 1991, pp. 50-54.
-
(1991)
Proc. European Conf
, pp. 50-54
-
-
Fujita, M.1
Matsunaga, Y.2
Kakuda, T.3
-
23
-
-
85009398482
-
Analysis and manipulation of Boolean functions in terms of decision graphs
-
J. Gergov and C. Meinel, “Analysis and manipulation of Boolean functions in terms of decision graphs,” in WG’92, LNCS, pp. 310-320, 1992.
-
(1992)
WG’92, LNCS
, pp. 310-320
-
-
Gergov, J.1
Meinel, C.2
-
24
-
-
0027590161
-
On the exact ordered binary decision diagram size of totally symmetric functions
-
M. Heap, “On the exact ordered binary decision diagram size of totally symmetric functions,” J. Electron. Testing: Theory and Applicat., vol. 4, pp. 191-195, 1993.
-
(1993)
J. Electron. Testing: Theory and Applicat
, vol.4
, pp. 191-195
-
-
Heap, M.1
-
25
-
-
0002599293
-
Detection of symmetries in combinatorial functions by spectral means
-
S. L. Hurst, “Detection of symmetries in combinatorial functions by spectral means,” IEE Electron. Circuits Syst., vol. 5, pp. 173-180, 1977.
-
(1977)
IEE Electron. Circuits Syst
, vol.5
, pp. 173-180
-
-
Hurst, S.L.1
-
26
-
-
0027091090
-
Minimization of binary decision diagrams based on exchange of variables
-
CAD, Nov
-
N. Ishiura, H. Sawada, and S. Yajima, “Minimization of binary decision diagrams based on exchange of variables,” in Proc. Int. Conf. CAD, Nov. 1991, pp. 472-475.
-
(1991)
Proc. Int. Conf
, pp. 472-475
-
-
Ishiura, N.1
Sawada, H.2
Yajima, S.3
-
27
-
-
0026138575
-
Multilevel logic synthesis of symmetric switching functions
-
B.-G. Kim and D. L. Dietmeyer, “Multilevel logic synthesis of symmetric switching functions,” IEEE Trans. Computer-Aided Design, vol. 10, no. 4, 1991.
-
(1991)
IEEE Trans. Computer-Aided Design
, vol.10
, Issue.4
-
-
Kim, B.-G.1
Dietmeyer, D.L.2
-
28
-
-
0028483037
-
EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition
-
Y.-T. Lai, M. Pedram, and S. B. K. Vrudhula, “EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition,” IEEE Trans. Computer-Aided Design, vol. 13, no. 8, pp. 959-975, 1994.
-
(1994)
IEEE Trans. Computer-Aided Design
, vol.13
, Issue.8
, pp. 959-975
-
-
Lai, Y.-T.1
Pedram, M.2
Vrudhula, S.B.K.3
-
29
-
-
0001117652
-
Boolean matching using binary decision diagrams with applications to logic synthesis and verification
-
Nov
-
Y.-T. Lai, S. Sastry, and M. Pedram, “Boolean matching using binary decision diagrams with applications to logic synthesis and verification,” in Proc. Int. Conf. CAD, Nov. 1992, pp. 452-458.
-
(1992)
Proc. Int. Conf. CAD
, pp. 452-458
-
-
Lai, Y.-T.1
Sastry, S.2
Pedram, M.3
-
30
-
-
84903828974
-
Representation of switching circuits by binary decision diagrams
-
C. Y. Lee, “Representation of switching circuits by binary decision diagrams,” Bell Syst. Tech. J., vol. 38, pp. 985-999, 1959.
-
(1959)
Bell Syst. Tech. J
, vol.38
, pp. 985-999
-
-
Lee, C.Y.1
-
31
-
-
0029707773
-
Least upper bounds on the sizes of symmetric variable order based OBDD’s
-
L. Litan, P. Molitor, and D. Möller, “Least upper bounds on the sizes of symmetric variable order based OBDD’s,” in Proc. Great Lakes Symp. VLSI, 1996, pp. 126-129.
-
(1996)
Proc. Great Lakes Symp. VLSI
, pp. 126-129
-
-
Litan, L.1
Molitor, P.2
Möller, D.3
-
32
-
-
85061355883
-
Technology mapping using Boolean matching and don’t care sets
-
Feb
-
F. Mailhot and G. De Micheli, “Technology mapping using Boolean matching and don’t care sets,” in Proc. European Conf. Design Automation, Feb. 1990, pp. 212-216.
-
(1990)
Proc. European Conf. Design Automation
, pp. 212-216
-
-
Mailhot, F.1
De Micheli, G.2
-
33
-
-
0024172602
-
Logic verification using binary decision diagrams in a logic synthesis environment
-
Nov
-
S. Malik, A. R. Wang, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Logic verification using binary decision diagrams in a logic synthesis environment,” in Proc. Int. Conf. CAD, Nov. 1988, pp. 6-9.
-
(1988)
Proc. Int. Conf. CAD
, pp. 6-9
-
-
Malik, S.1
Wang, A.R.2
Brayton, R.K.3
Sangiovanni-Vincentelli, A.L.4
-
34
-
-
0002751625
-
Permutation and phase independent Boolean comparison
-
Design Automation, Feb
-
J. Mohnke and S. Malik, “Permutation and phase independent Boolean comparison,” in Proc. European Conf. Design Automation, Feb. 1993, pp. 86-92.
-
(1993)
Proc. European Conf
, pp. 86-92
-
-
Mohnke, J.1
Malik, S.2
-
35
-
-
0029507888
-
Limits of using signatures for permutation independent Boolean comparison
-
Aug
-
J. Mohnke, P. Molitor, and S. Malik, “Limits of using signatures for permutation independent Boolean comparison,” in Proc. ASP Design Automation Conf., Aug. 1995, pp. 459-464.
-
(1995)
Proc. ASP Design Automation Conf
, pp. 459-464
-
-
Mohnke, J.1
Molitor, P.2
Malik, S.3
-
36
-
-
0027841575
-
Detection of symmetry of Boolean functions represented as ROBDD’s
-
Nov
-
D. Möller, J. Mohnke, and M. Weber, “Detection of symmetry of Boolean functions represented as ROBDD’s,” in Proc. Int. Conf. CAD, Nov. 1993, pp. 680-684.
-
(1993)
Proc. Int. Conf. CAD
, pp. 680-684
-
-
Möller, D.1
Mohnke, J.2
Weber, M.3
-
37
-
-
0002148042
-
Symmetry based variable ordering for ROBDD’s
-
Dec
-
D. Möller, P. Molitor, and R. Drechsler, “Symmetry based variable ordering for ROBDD’s,” in Proc. IFIP Workshop on Logic and Architecture Synthesis, Dec. 1994, pp. 47-53.
-
(1994)
Proc. IFIP Workshop on Logic and Architecture Synthesis
, pp. 47-53
-
-
Möller, D.1
Molitor, P.2
Drechsler, R.3
-
38
-
-
84976709337
-
Decision trees and diagrams
-
B. M. E. Moret, “Decision trees and diagrams,” in Comput. Surveys, vol. 14, pp. 593-623, 1982.
-
(1982)
Comput. Surveys
, vol.14
, pp. 593-623
-
-
Moret, B.M.E.1
-
39
-
-
85009380514
-
-
Tech. Rep. CoSc-1992-2, Texas Christian Univ., Fort Worth, TX
-
C. Morgenstern, “A new backtracking heuristic for rapidly four-coloring large planar graphs,” Tech. Rep. CoSc-1992-2, Texas Christian Univ., Fort Worth, TX, 1992.
-
(1992)
A New Backtracking Heuristic for Rapidly Four-Coloring Large Planar Graphs
-
-
Morgenstern, C.1
-
40
-
-
0029487141
-
Who are the variables in your neighborhood
-
CAD, Nov
-
S. Panda and F. Somenzi, “Who are the variables in your neighborhood,” in Proc. Int. Conf. CAD, Nov. 1995, pp. 74-77.
-
(1995)
Proc. Int. Conf
, pp. 74-77
-
-
Panda, S.1
Somenzi, F.2
-
41
-
-
0028712919
-
Symmetry detection and dynamic variable ordering of decision diagrams
-
CAD, Nov
-
S. Panda, F. Somenzi, and B. F. Plessier, “Symmetry detection and dynamic variable ordering of decision diagrams,” in Proc. Int. Conf. CAD, Nov. 1994, pp. 628-631.
-
(1994)
Proc. Int. Conf
, pp. 628-631
-
-
Panda, S.1
Somenzi, F.2
Plessier, B.F.3
-
42
-
-
0028087504
-
On determining symmetries in inputs of logic circuits
-
Jan
-
I. Pomeranz and S. M. Reddy, “On determining symmetries in inputs of logic circuits,” in VLSI Design Conf., Jan. 1994, pp. 255-260.
-
(1994)
VLSI Design Conf
, pp. 255-260
-
-
Pomeranz, I.1
Reddy, S.M.2
-
43
-
-
0027841555
-
Dynamic variable ordering for ordered binary decision diagrams
-
Nov
-
R. Rudell, “Dynamic variable ordering for ordered binary decision diagrams,” in Proc. Int. Conf. CAD, Nov. 1993, pp. 42-47.
-
(1993)
Proc. Int. Conf. CAD
, pp. 42-47
-
-
Rudell, R.1
-
44
-
-
0030686693
-
Minimizing ROBDD sizes of incompletely specified functions by exploiting strong symmetries
-
Mar
-
C. Scholl, S. Melchior, G. Hotz, and P. Molitor, “Minimizing ROBDD sizes of incompletely specified functions by exploiting strong symmetries,” in Proc. European Design & Test Conf., Mar. 1997, pp. 229-234.
-
(1997)
Proc. European Design & Test Conf
, pp. 229-234
-
-
Scholl, C.1
Melchior, S.2
Hotz, G.3
Molitor, P.4
-
45
-
-
0029486766
-
Communication based FPGA synthesis for multi-output Boolean functions
-
Aug
-
C. Scholl and P. Molitor, “Communication based FPGA synthesis for multi-output Boolean functions,” in Proc. ASP Design Automation Conf., Aug. 1995, pp. 279-287.
-
(1995)
Proc. ASP Design Automation Conf
, pp. 279-287
-
-
Scholl, C.1
Molitor, P.2
-
46
-
-
0003934798
-
-
Tech. Rep., Univ. Berkeley, Berkeley, CA
-
E. Sentovich, K. Singh, L. Lavagno, Ch. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli, “SIS: A system for sequential circuit synthesis,” Tech. Rep., Univ. Berkeley, Berkeley, CA, 1992.
-
(1992)
SIS: A System for Sequential Circuit Synthesis
-
-
Sentovich, E.1
Singh, K.2
Lavagno, L.3
Moon, C.H.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.8
Brayton, R.9
Sangiovanni-Vincentelli, A.10
-
47
-
-
0028583842
-
Heuristic minimization of BDD’s using don’t cares
-
June
-
T. R. Shiple, R. Hojati, A. L. Sangiovanni-Vincentelli, and R. K. Brayton, “Heuristic minimization of BDD’s using don’t cares,” in Proc. Design Automation Conf., June 1994, pp. 225-231.
-
(1994)
Proc. Design Automation Conf
, pp. 225-231
-
-
Shiple, T.R.1
Hojati, R.2
Sangiovanni-Vincentelli, A.L.3
Brayton, R.K.4
-
48
-
-
85009408844
-
Variable orderings and the size of OBDD’s for partially symmetric Boolean functions
-
Nov
-
D. Sieling, “Variable orderings and the size of OBDD’s for partially symmetric Boolean functions,” in SASIMI, pp. 189-196, Nov. 1996.
-
(1996)
SASIMI
, pp. 189-196
-
-
Sieling, D.1
-
49
-
-
0021471021
-
Optimal decision trees and one-time-only branching programs for symmetric Boolean functions
-
I. Wegener, “Optimal decision trees and one-time-only branching programs for symmetric Boolean functions,” Inform., Contr., vol. 62, pp. 129-143, 1984.
-
(1984)
Inform., Contr
, vol.62
, pp. 129-143
-
-
Wegener, I.1
-
50
-
-
0029215231
-
Functional multiple-output decomposition: Theory and implicit algorithm
-
June
-
B. Wurth, K. Eckl, and K. Antreich, “Functional multiple-output decomposition: Theory and implicit algorithm,” in Proc. Design Automation Conf., June 1995, pp. 54-59.
-
(1995)
Proc. Design Automation Conf
, pp. 54-59
-
-
Wurth, B.1
Eckl, K.2
Antreich, K.3
|