SCOPUS 정보 검색 플랫폼

Volumn 10, Issue 1-2, 2000, Pages 101-111

Decomposition of bus-invert coding for low-power I/O

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0003292625 PISSN: 02181266 EISSN: None Source Type: Journal
DOI: 10.1016/s0218-1266(00)00009-3 Document Type: Article

Times cited : (13)

References (11)

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2
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3
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- Bus-invert coding for low-power I/O
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4
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- Liu, D.¹ Svensson, C.²

5
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- Saving power in the control path of embedded processors
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6
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- Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
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7
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- System-level power optimization of special purpose applications, the beach solution
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- Benni, L.¹ De Micheli, G.² Macii, E.³ Poncino, M.⁴ Quer, S.⁵

8
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- Reduction of bus transitions with partial bus-invert coding
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9
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