An integrated data path optimization for low power based on network flow method

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 553-559

  Lyuh, C G ^a   Kim, T ^a   Liu, C L ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; OPTIMIZATION; POWER CONTROL; SCHEDULING; SWITCHING;

NETWORK FLOW METHOD;

VLSI CIRCUITS;

EID: 0035215649     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. High-level power modeling, estimation, and optimization
2. A survey of design technique for system-level dynamic power management
3. Scheduling and resource binding for low power
4. Scheduling technique to enable power management
5. SCALP: An iterative improvement based low-power data path synthesis system
6. Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
7. High-reliability, low-energy microarchitecture synthesis
8. Bus optimization for low-power data path synthesis based on network flow method
9. Register allocation and binding for low power
10. Module assignment for low power
11. Low-power memory mapping through reducing address bus activity
12. Bus-invert coding for low power I/O
13. A coding framework for low-power address and data busses
14. Transition density, a stochastic measure of activity in digital circuits