Lateral design of InP/InGaAs DHBTs for 40 Gbit/s ICs

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Volumn , Issue , 2000, Pages 481-484

  Blayac, S ^a   Riet, M ^a   Benchimol, J L ^a   Berdaguer, P ^a   Kauffman, N ^a   Godin, J ^a   Scavennec, A ^a  

^a ORANGE LABS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE HETEROJUNCTION BIPOLAR TRANSISTORS (DHBT);

INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SEMICONDUCTING INDIUM GALLIUM ARSENIDE;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0033690211     PISSN: 10928669     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)

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7. Minoru Ida. Shoji Yamahata. Hiroki Nakajima. Niriyuki Watanabe. "High performance small InP/lnGaAs HBTs with reduced parasitic base-collector capacitance fabricated using a novel base metal design", in Proc. of ISCS. Berlin, 22-26 August 99.