Limits to voltage scaling from the low power perspective

Proceedings - 13th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2000, Pages 365-370

  Forestier, A ^a   Stan, M R ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF VIRGINIA   (United States)

Author keywords

Analytical models; Circuit simulation; Circuit synthesis; CMOS technology; Dynamic voltage scaling; Logic design; Manufacturing; Power dissipation; Power supplies; Threshold voltage

Indexed keywords

ANALYTICAL MODELS; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRIC LOSSES; ELECTRIC NETWORK ANALYSIS; ENERGY DISSIPATION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LOGIC DESIGN; MANUFACTURE; SYSTEMS ANALYSIS; THRESHOLD VOLTAGE; VOLTAGE SCALING;

CIRCUIT DESIGN TECHNIQUES; CIRCUIT SYNTHESIS; CMOS TECHNOLOGY; DYNAMIC POWER DISSIPATION; EXTENSIVE SIMULATIONS; FIRST-ORDER ANALYSIS; POWER SUPPLY; POWER SUPPLY VOLTAGE;

LOGIC CIRCUITS;

EID: 84951853162     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2000.876056     Document Type: Conference Paper

References (9)

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