The high-bandwidth 256 kB 2nd level cache on an Itanium Microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 418-478

  Riedlinger, Reid ^a   Grutkowski, Tom ^b  

^a HEWLETT PACKARD COMPANY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; BANDWIDTH; BUFFER STORAGE; DATA REDUCTION; DIGITAL ARITHMETIC; QUEUEING NETWORKS; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

DATA ARRAY IMPLEMENTATION;

MICROPROCESSOR CHIPS;

EID: 0036117401     PISSN: 01936530     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISSCC.2002.993110     Document Type: Article

References (0)