Evaluation of CORDIC algorithms for FPGA design

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 32, Issue 3, 2002, Pages 207-222

  Valls, Javier ^a   Kuhlmann, Martin ^b   Parhi, Keshab K ^b  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b BROADCOM CORPORATION   (United States)

Author keywords

CORDIC; FPGA; Redundant arithmetic; Two's complement

Indexed keywords

ALGORITHMS; DIGITAL ARITHMETIC; DIGITAL COMPUTERS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; MATHEMATICAL OPERATORS;

COORDINATE ROTATION DIGITAL COMPUTER; REDUNDANT ARITHMETIC OPERATORS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036842597     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1020205217934     Document Type: Article

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