Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 20, Issue 3, 1998, Pages 267-278

  Hsiao, Shen Fu ^a,b,c,d   Chen, Jen Yin ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^d YALE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; DIGITAL COMPUTERS; ERROR ANALYSIS; INPUT OUTPUT PROGRAMS; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS; ADDERS; ALGORITHMS; CALCULATIONS; COMPUTER HARDWARE; FUNCTIONS; ITERATIVE METHODS; REDUNDANCY; VECTORS;

COORDINATE ROTATION DIGITAL COMPUTER (CORDIC); CELL LIBRARY; CONSTANT SCALING FACTOR; ROTATION METHODS; SQUARE-ROOT OPERATIONS;

DIGITAL SIGNAL PROCESSING; PROGRAM PROCESSORS;

EID: 0032320942     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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