Trench isolation step-induced (TRISI) narrow width effect on MOSFET

IEEE Electron Device Letters

Volumn 23, Issue 10, 2002, Pages 600-602

  Kim, Youngmin ^a,b,c   Sridhar, Seetharaman ^a,b   Chatterjee, Amitava ^a,b  

^a Texas Instruments ^*

^b TEXAS INSTRUMENTS   (United States)

^c Hong Ik University   (South Korea)

Author keywords

Mismatch; MOSFET; Shallow trench isolation (STI)

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MATHEMATICAL MODELS; POLYSILICON; PROCESS CONTROL; SEMICONDUCTOR DEVICE MANUFACTURE; THRESHOLD VOLTAGE;

MISMATCH; SHALLOW TRENCH ISOLATION; TRENCH ISOLATION STEP-INDUCED NARROW WIDTH EFFECT;

MOSFET DEVICES;

EID: 0036803359     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

1. L. Akers, "The inverse narrow-width effect," IEEE Electron Device Lett., vol. 7, pp. 419-421, July 1986.
2. G. Scotts, J. Lutze, M. Rubin, F. Nouri, and M. Manley, "NMOS drive current reduction caused by transistor layout and trench isolation induced stress," in IEDM Tech. Dig., 1999, pp. 827-830.
3. G. Fuse, M. Fukumoto, A. Shinohara, S. Odanaka, M. Sasago, and T. Ohzone, "A new isolation method with Boron-implanted side-walls for controlling narrow-width effect," IEEE Trans. Electron Devices, vol. ED-34, pp. 356-360, Feb. 1987.
4. J. Kim, T. Kim, J. Park, W. Kim, B. Hong, and G. Yoon, "A shallow trench isolation using Nitric Oxide (NO)-annealed wall oxide to suppress inverse narrow width effect," IEEE Electron Device Lett., vol. 21, pp. 575-577, Dec. 2000.
5. M. Mehrotra, J. Hu, A. Jain, W. Shiau, V. Reddy, S. Aur, and M. Rodder, "A 1.2 V, sub-0.09 mm gate length CMOS technology," in IEDM Tech. Dig., 1999, pp. 419-422.
6. A. Chatterjee, I. Ali, K. Joyner, D. Mercer, J. Kuehne, M. Mason, A. Esquivel, D. Rogers, S. O'Brien, P. Mei, S. Murtaza, S. Kwok, K. Talyor, S. Nag, G. Hames, M. Hanratty, H. Marchman, S. Ashburn, and I. Chen, "Integration of unit processes in a shallow trench isolation module for a 0.25 μm CMOS technology," J. Vac. Sci. Technol. B, vol. 15, pp. 1936-1942, 1997.
7. H. Tuinhout, A. Montree, J. Schmitz, and P. Stolk, "Effects of gate depletion and Boron penetration on matching of deep submicron CMOS transistor," in IEDM Tech. Dig., 1997, pp. 631-634.
8. A. Asenov and S. Saini, "Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide," IEEE Trans. Electron Devices, vol. 47, pp. 805-812, Apr. 2000.