Shallow trench isolation using nitric oxide (NO)-annealed wall oxide to suppress inverse narrow width effect

IEEE Electron Device Letters

Volumn 21, Issue 12, 2000, Pages 575-577

  Kim, Jongoh ^a   Kim, Taewoo ^a   Park, Jaebeom ^a   Kim, Woojin ^a   Hong, Byungseop ^a   Yoon, Gyuhan ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; BORON; DIFFUSION; NITROGEN COMPOUNDS; OXIDATION;

INVERSE NARROW WIDTH EFFECT (INWE);

TRANSISTORS;

EID: 0034511130     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.887470     Document Type: Article

References (10)

1. S. K. H. Fung, M. Chan, and P. K. Ko, "Inverse-narrow-width effect of deep sub-micrometer MOSFET's with LOCOS isolation," Solid-State Electron., vol. 41, pp. 1885-1889, 1997.
2. E. H. Li, K. M. Homg, Y. C. Cheng, and K. Y. Chan, "The narrow-channel effect in MOSFET's with semi-recessed oxide structures," IEEE Trans. Electron Devices, vol. 37, pp. 692-701, Mar. 1990.
3. A. Ono, R. Ueno, and I. Sakai, "TED control technology for suppression of reverse narrow channel effect in 0.1 μm MOS devices," in IEDM Tech. Dig., 1997, pp. 227-230.
4. A. Chatterjee et al., "A shallow trench isolation using LOCOS edge for preventing comer effects for 0.25/0.18 μm CMOS technologies and beyond," in IEDM Tech. Dig., 1996, pp. 829-832.
5. C. Chen, J. W. Chou, W. Lur, and S. W. Sun, "A novel 0.25 μm shallow trench isolation technology," in IEDM Tech. Dig., 1996, pp. 837-840.
6. G. Fuse et al., "A new isolation method with boron-implanted sidewalls for controlling narrow-width effect," IEEE Trans. Electron Devices, vol. ED-34, pp. 356-360, Feb. 1987.
7. W. K. Yeh, T. Lin, C. Chen, and S. W. Sun. "A novel shallow trench isolation with mini-spacer technology," in SSDM Proc., 1998, pp. 98-99.
8. T. Kim, J. Kim, and J. Om, "A novel shallow trench isolation to control inverse narrow width effect on CMOS transistor," J. Korean Phys. Soc., vol. 35, pp. 861-864, Dec. 1999.
9. M. S. C. Luo et al., "0.25 μm CMOS technology with 45 A NO-nitrided oxide," in IEDM Tech. Dig., 1995, pp. 691-694.
10. T. Morimoto et al., "Effects of boron penetration and resultant limitations in ultra thin pure-oxide and nitrided-oxide gate films," in IEDM Tech. Dig., 1990, pp. 429-432.