Multiple-valued T-gate based on multiple junction surface tunnel transistor

IEICE Transactions on Electronics

Volumn E85-C, Issue 7, 2002, Pages 1486-1490

  Uemura, Tetsuya ^a   Baba, Toshio ^b  

^a HOKKAIDO UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

Flip flop; Multiple valued logic; NDR; T gate; Tunnel transistor

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; FLIP FLOP CIRCUITS; RESONANT TUNNELING; ULSI CIRCUITS;

TUNNEL TRANSISTORS;

GATES (TRANSISTOR);

EID: 0036631230     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (10)

1. Resonant tunneling device with multiple negative differential resistance: Digital and signal applications with reduced circuit complexity
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3. Proposal for surface tunnel transistors
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5. Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits
6. Development of quantum functional devices for multiple-valued logic circuits
7. New resonant tunneling logic gate employing monostable-bistable transition
8. 0.47As-based surface tunnel transistors
9. Fabrication of self-aligned surface tunnel transistors with a 80-nm gate length