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Volumn 10, Issue 3, 2002, Pages 230-239

Microarchitecture-level power management

Author keywords

Energy aware computing; Power management; Resource scaling; Voltage scaling

Indexed keywords

MICROARCHITECTURE; POWER MANAGEMENT;

EID: 0036625425     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.1043326     Document Type: Article
Times cited : (15)

References (23)
  • 4
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    • Advanced configuration and power interface specification
    • Compaq, Intel, Microsoft, Phoenix and Toshiba
    • "Advanced Configuration and Power Interface Specification," Compaq, Intel, Microsoft, Phoenix and Toshiba, http://www.acpi.info/spec.htm, 2000.
    • (2000)
  • 9
    • 0030206510 scopus 로고    scopus 로고
    • Instruction level power analysis and optimization of software
    • V. Tiwari, S. Malik, A. Wolfe, and M. Lee, "Instruction level power analysis and optimization of software," J. VLSI Signal Processing, vol. 13, no. 1-2, 1996.
    • (1996) J. VLSI Signal Processing , vol.13 , Issue.1-2
    • Tiwari, V.1    Malik, S.2    Wolfe, A.3    Lee, M.4
  • 18
    • 0003926726 scopus 로고    scopus 로고
    • Quantifying the complexity of superscalar processors
    • University of Wisconsin-Madison, Dept. Comput. Sci., Tech. Rep. 1328
    • S. Palacharla, N. P. Jouppi, and J. E. Smith, "Quantifying the Complexity of Superscalar Processors," University of Wisconsin-Madison, Dept. Comput. Sci., Tech. Rep. 1328, 1996.
    • (1996)
    • Palacharla, S.1    Jouppi, N.P.2    Smith, J.E.3
  • 20
    • 0003465202 scopus 로고    scopus 로고
    • The simplescalar tool set, version 2.0
    • Univ. Wisconsin-Madison, Dept. Comput. Sci., Tech. Rep. 1342
    • D. Burger and T. M. Austin, "The Simplescalar Tool Set, Version 2.0," Univ. Wisconsin-Madison, Dept. Comput. Sci., Tech. Rep. 1342, 1997.
    • (1997)
    • Burger, D.1    Austin, T.M.2
  • 21
    • 0003650381 scopus 로고
    • An enhanced access and cycle time model for on-chip caches
    • Western Res. Lab., DEC, Tech. Rep. 93/5
    • S. J. E. Wilton and N. P. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," Western Res. Lab., DEC, Tech. Rep. 93/5, 1994.
    • (1994)
    • Wilton, S.J.E.1    Jouppi, N.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.