-
1
-
-
0033358774
-
System-level power optimization: Techniques and tools
-
L. Benini and G. de Micheli, "System-level power optimization: Techniques and tools," in Proc. Int. Symp. Low-Power Electronics Design, San Diego, CA, Aug. 1999, pp. 288-293.
-
Proc. Int. Symp. Low-Power Electronics Design, San Diego, CA, Aug. 1999
, pp. 288-293
-
-
Benini, L.1
De Micheli, G.2
-
2
-
-
0033363851
-
Using dynamic cache management techniques to reduce energy in a high-performance processor
-
N. Bellas, I. Hajj, and C. Polychronopoulos, "Using dynamic cache management techniques to reduce energy in a high-performance processor," in Proc. Int. Symp. Low-Power Electronics Design, San Diego, CA, Aug. 1999, pp. 64-69.
-
Proc. Int. Symp. Low-Power Electronics Design, San Diego, CA, Aug. 1999
, pp. 64-69
-
-
Bellas, N.1
Hajj, I.2
Polychronopoulos, C.3
-
3
-
-
0033358971
-
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
-
K. Ghose and M. B. Kamble, "Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation," in Proc. Int. Symp. Low-Power Electronics and Design, San Diego, CA, Aug. 1999, pp. 70-75.
-
Proc. Int. Symp. Low-Power Electronics and Design, San Diego, CA, Aug. 1999
, pp. 70-75
-
-
Ghose, K.1
Kamble, M.B.2
-
4
-
-
0003722586
-
Advanced configuration and power interface specification
-
Compaq, Intel, Microsoft, Phoenix and Toshiba
-
"Advanced Configuration and Power Interface Specification," Compaq, Intel, Microsoft, Phoenix and Toshiba, http://www.acpi.info/spec.htm, 2000.
-
(2000)
-
-
-
5
-
-
0031639466
-
The simulation and evaluation of dynamic voltage scaling algorithms
-
T. Pering and R. Brodersen, "The simulation and evaluation of dynamic voltage scaling algorithms," in Proc. Int. Symp. Low-Power Electronics Design, Monterey, CA, Aug. 1998, pp. 76-81.
-
Proc. Int. Symp. Low-Power Electronics Design, Monterey, CA, Aug. 1998
, pp. 76-81
-
-
Pering, T.1
Brodersen, R.2
-
7
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis and optimizations
-
D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Proc. Int. Symp. Comput. Architecture (ISCA), Vancouver, Canada, May 2000, pp. 83-94.
-
Proc. Int. Symp. Comput. Architecture (ISCA), Vancouver, Canada, May 2000
, pp. 83-94
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
8
-
-
0033712191
-
The design and use of simplepower: A cycle-accurate energy estimation tool
-
W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "The design and use of simplepower: A cycle-accurate energy estimation tool," in Proc. 37th Design Automation Conf., May 2000, pp. 95-106.
-
Proc. 37th Design Automation Conf., May 2000
, pp. 95-106
-
-
Ye, W.1
Vijaykrishnan, N.2
Kandemir, M.3
Irwin, M.J.4
-
9
-
-
0030206510
-
Instruction level power analysis and optimization of software
-
V. Tiwari, S. Malik, A. Wolfe, and M. Lee, "Instruction level power analysis and optimization of software," J. VLSI Signal Processing, vol. 13, no. 1-2, 1996.
-
(1996)
J. VLSI Signal Processing
, vol.13
, Issue.1-2
-
-
Tiwari, V.1
Malik, S.2
Wolfe, A.3
Lee, M.4
-
10
-
-
0031594012
-
Pipeline gating: Speculation control for energy reduction
-
S. Manne, A. Klauser, and D. Grunwald, "Pipeline gating: Speculation control for energy reduction," in Proc. Int. Symp. Computer. Architecture (ISCA), Barcelona, Spain, May 1998, pp. 132-141.
-
Proc. Int. Symp. Computer. Architecture (ISCA), Barcelona, Spain, May 1998
, pp. 132-141
-
-
Manne, S.1
Klauser, A.2
Grunwald, D.3
-
11
-
-
0033645908
-
Profile driven code execution for low power dissipation
-
D. Marculescu, "Profile driven code execution for low power dissipation," in Proc. Int. Symp. Low-Power Electronics Design, Rapallo, Portofino, Spain, Aug. 2000, pp. 253-255.
-
Proc. Int. Symp. Low-Power Electronics Design, Rapallo, Portofino, Spain, Aug. 2000
, pp. 253-255
-
-
Marculescu, D.1
-
12
-
-
0033658512
-
Optimization of high-performance superscalar architectures for energy-delay product
-
V. Zyuban and P. Kogge, "Optimization of high-performance superscalar architectures for energy-delay product," in Proc. Int. Symp. Low-Power Electronics Design, Rapallo, Portofino, Spain, Aug. 2000, pp. 84-89.
-
Proc. Int. Symp. Low-Power Electronics Design, Rapallo, Portofino, Spain, Aug. 2000
, pp. 84-89
-
-
Zyuban, V.1
Kogge, P.2
-
13
-
-
0031594003
-
Dynamic ipc/clock rate optimization
-
D. H. Albonesi, "Dynamic ipc/clock rate optimization," in Proc. Int. Symp. Comput. Architecture (ISCA), Barcelona, Spain, May 1998, pp. 282-292.
-
Proc. Int. Symp. Comput. Architecture (ISCA), Barcelona, Spain, May 1998
, pp. 282-292
-
-
Albonesi, D.H.1
-
14
-
-
0034839435
-
Power and energy reduction via pipeline balancing
-
R. I. Bahar and S. Manne, "Power and energy reduction via pipeline balancing," in Proc. Int. Symp. Comput. Architecture, Goteborg, Sweden, May 2001, pp. 218-229.
-
Proc. Int. Symp. Comput. Architecture, Goteborg, Sweden, May 2001
, pp. 218-229
-
-
Bahar, R.I.1
Manne, S.2
-
15
-
-
0034838829
-
Energy-effective issue logic
-
D. Folegnani and A. Gonzalez, "Energy-effective issue logic," in Proc. Int. Symp. Comput. Architecture (ISCA), Goteborg, Sweden, May 2001, 230-239
-
Proc. Int. Symp. Comput. Architecture (ISCA), Goteborg, Sweden, May 2001
, pp. 230-239
-
-
Folegnani, D.1
Gonzalez, A.2
-
16
-
-
0013035133
-
Using IPC variation in workloads with externally specified rates to reduce power consumption
-
S. Ghiasi, J. Casmira, and D. Grunwald, "Using IPC variation in workloads with externally specified rates to reduce power consumption," in Proc. Workshop Complexity Effective Design, Vancouver, Canada, May 2000.
-
Proc. Workshop Complexity Effective Design, Vancouver, Canada, May 2000
-
-
Ghiasi, S.1
Casmira, J.2
Grunwald, D.3
-
17
-
-
0032629113
-
A hardware-driven profiling scheme for identifying program hotspots to support runtime optimization
-
M. C. Merten, A. R. Trick, C. N. George, J. C. Gyllenhaal, and W. W. Hwu, "A hardware-driven profiling scheme for identifying program hotspots to support runtime optimization," in Proc. Int. Symp. Comput. Architecture (ISCA), Atlanta, GA, May 1999, pp. 136-148.
-
Proc. Int. Symp. Comput. Architecture (ISCA), Atlanta, GA, May 1999
, pp. 136-148
-
-
Merten, M.C.1
Trick, A.R.2
George, C.N.3
Gyllenhaal, J.C.4
Hwu, W.W.5
-
18
-
-
0003926726
-
Quantifying the complexity of superscalar processors
-
University of Wisconsin-Madison, Dept. Comput. Sci., Tech. Rep. 1328
-
S. Palacharla, N. P. Jouppi, and J. E. Smith, "Quantifying the Complexity of Superscalar Processors," University of Wisconsin-Madison, Dept. Comput. Sci., Tech. Rep. 1328, 1996.
-
(1996)
-
-
Palacharla, S.1
Jouppi, N.P.2
Smith, J.E.3
-
19
-
-
0029193696
-
Clustered voltage scaling technique for low-power design
-
K. Usami, and M. Horowitz, "Clustered voltage scaling technique for low-power design," in Proc. Workshop Low-Power Design, Monterey, CA, Aug. 1995, pp. 3-8.
-
Proc. Workshop Low-Power Design, Monterey, CA, Aug. 1995
, pp. 3-8
-
-
Usami, K.1
Horowitz, M.2
-
20
-
-
0003465202
-
The simplescalar tool set, version 2.0
-
Univ. Wisconsin-Madison, Dept. Comput. Sci., Tech. Rep. 1342
-
D. Burger and T. M. Austin, "The Simplescalar Tool Set, Version 2.0," Univ. Wisconsin-Madison, Dept. Comput. Sci., Tech. Rep. 1342, 1997.
-
(1997)
-
-
Burger, D.1
Austin, T.M.2
-
21
-
-
0003650381
-
An enhanced access and cycle time model for on-chip caches
-
Western Res. Lab., DEC, Tech. Rep. 93/5
-
S. J. E. Wilton and N. P. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," Western Res. Lab., DEC, Tech. Rep. 93/5, 1994.
-
(1994)
-
-
Wilton, S.J.E.1
Jouppi, N.P.2
-
22
-
-
0031339427
-
Mediabench: A tool for evaluating and synthesizing multimedia and communications systems
-
C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "Mediabench: A tool for evaluating and synthesizing multimedia and communications systems," in Proc. Int. Symp. Microarchitecture (Micro), Research Triangle Park, NC, Dec. 1997, pp. 330-335.
-
Proc. Int. Symp. Microarchitecture (Micro), Research Triangle Park, NC, Dec. 1997
, pp. 330-335
-
-
Lee, C.1
Potkonjak, M.2
Mangione-Smith, W.H.3
-
23
-
-
0030685015
-
Thermal management system for high performance powerPC microprocessors
-
H. Sanchez, B. Kuttanna, T. Olson, M. Alexander, G. Gerosa, R. Philip, and J. Alvarez, "Thermal Management System for High Performance PowerPC Microprocessors," in Proc. IEEE CompCon, San Jose, CA, Feb. 1997, pp. 325-330.
-
Proc. IEEE CompCon, San Jose, CA, Feb. 1997
, pp. 325-330
-
-
Sanchez, H.1
Kuttanna, B.2
Olson, T.3
Alexander, M.4
Gerosa, G.5
Philip, R.6
Alvarez, J.7
|