Layout design on bond pads to improve the firmness of bond wire in packaged IC products

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 1999, Pages 147-150

  Peng, Jeng Jie ^a   Ker, Ming Dou ^a   Wang, Nien Ming ^a   Jiang, Hsin Chin ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; RELIABILITY; SUBSTRATES;

BALL SHEAR TEST; BOND PAD; BOND WIRE; WIRE PULL TEST;

WIRE;

EID: 0032599234     PISSN: 1524766X     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (14)