Silicon resonant tunneling metal-oxide-semiconductor transistor for sub-0.1 μm era

IEICE Transactions on Electronics

Volumn E85-C, Issue 5, 2002, Pages 1086-1090

  Matsuo, Naoto ^a   Takami, Yoshinori ^a   Nozaki, Takahiro ^a   Hamada, Hiroki ^b  

^a YAMAGUCHI UNIVERSITY   (Japan)

^b SANYO ELECTRIC CO LTD   (Japan)

Author keywords

Logic circuit; SRTMOST; Sub 0.1 m

Indexed keywords

CURRENT DENSITY; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC INVERTERS; LOGIC CIRCUITS; RESONANT TUNNELING; SEMICONDUCTING SILICON; VOLTAGE MEASUREMENT;

DRAIN CURRENTS; DRAIN VOLTAGE; INVERTER CIRCUIT; SILICON RESONANT TUNNELING METAL OXIDE SEMICONDUCTOR TRANSISTOR;

MOSFET DEVICES;

EID: 0036579454     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

1. A folded-channel MOSFET for deep-sub-tenth micron era
2. Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
3. The ballistic nano-transistor
4. Transport properties in sub-10-nm-gate EJ-MOSFETs
5. Application of tunneling effect for thin dielectric film to MOS transistor
6. Simulation of Si resonant tunneling MOS transistor - Transconductance and subthreshold swing
7. Study of barrier-height of Si resonant tunneling MOS transistor (SRTMOST) - Relationship between barrier-height and gate length
8. Extension of physical limit of conventional metal-oxide-semiconductor transistor by double barriers formed at the channel edges
9. Influence of off-set energy on the electrical characteristics of Si resonant tunneling MOST (SRTMOST)
10. A tunneling-barrier junction SOI MOSFET with a suppressed short-channel effect for the ultimate device structure
11. 2 film