Digital window comparator DfT scheme for mixed-signal ICs

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 2, 2002, Pages 121-128

  De Venuto, Daniela ^a   Ohletz, Michael J ^b   Riccò, Bruno ^c  

^a POLITECNICO DI BARI   (Italy)

^b LUCENT TECHNOLOGIES   (United States)

^c UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

DfT; GO NOGO test; Mixed signal ASIC; Signal level evaluation; Window comparator

Indexed keywords

CAPACITANCE; COMPARATOR CIRCUITS; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; ELECTRIC LOADS;

MIXED-SIGNAL INTEGRATED CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0036535280     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1014937424827     Document Type: Article

References (9)

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5. Early capture for boundary scan timing measurements
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7. Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits
8. Fault dictionary based upon stimulus design