Analysis of stratified testing for multichip module systems

IEEE Transactions on Reliability

Volumn 51, Issue 1, 2002, Pages 100-110

  Park, Nohpill ^a   Lombardi, Fabrizio ^b  

^a Oklahoma State University   (United States)

^b Northeastern University   (United States)

Author keywords

Defect level; Known good yield; Multichip module; Quality assurance; Stratified testing

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; MARKOV PROCESSES; MATHEMATICAL MODELS; MONTE CARLO METHODS; QUALITY ASSURANCE; VLSI CIRCUITS;

DEFECT LEVEL; KNOWN GOOD YIELD; RANDOM TESTING; STRATIFIED TESTING; YIELD STRATUM FIRST TESTING;

MULTICHIP MODULES;

EID: 0036507956     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/24.994924     Document Type: Article

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