Integration of high-Q inductors in a latch-up resistant CMOS technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 757-760

  Frei, M R ^a   Belk, N R ^a   Dennis, D C ^a   Carroll, M S ^a   Lin, W ^a   Pinto, M R ^a   Archer, V D ^a   Ivanov, T G ^a   Moinian, S ^a   Ng, K K ^a   Chu, J ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; EDDY CURRENTS; ELECTRIC DISCHARGES; FLIP FLOP CIRCUITS; OPTIMIZATION; Q FACTOR MEASUREMENT; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; SUBSTRATES;

EDDY CURRENT LOSSES; HIGH Q INDUCTORS; LATCH UP RESISTANT;

ELECTRIC INDUCTORS;

EID: 0033314266     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)