A graph theoretic approach for synthesizing very low-complexity high-speed digital filters

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 2, 2002, Pages 204-216

  Muhammad, Khurram ^a   Roy, Kaushik ^b  

^a TEXAS INSTRUMENTS   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Computation reuse; Digital filters; High level synthesis; High performance; Low complexity; Low power; System level

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK SYNTHESIS; GRAPH THEORY; HAMILTONIANS; POLYNOMIALS; TABLE LOOKUP; THEOREM PROVING; TRANSFER FUNCTIONS; TRAVELING SALESMAN PROBLEM;

COMPUTATIONAL REDUNDANCY; DIFFERENTIAL COEFFICIENT METHOD; HAMILTONIAN PATH;

FIR FILTERS;

EID: 0036474435     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.980259     Document Type: Article

References (26)

1. FIRGEN: A computer-aided design system for high performance FIR filter integrated circuits
2. Design techniques for silicon compiler implementations of high-speed FIR digital filters
3. FIR filter design over a discrete powers-of-two coefficient space
4. Multiplierless realization of adaptive filters by nonuniform quantization of input signal
5. The design of low-complexity linear-phase FIR filter banks using powers-of-two coefficients with an application to subband image coding
6. The design of two-channel lattice structure perfect-reconstruction filter banks using powers-of-two coefficients
7. An improved search algorithm for the design of multiplier-less FIR filters with powers-of-two coefficients
8. Fast FIR digital filter structures using minimal number of adders and its application to filter design
9. Low-area/power parallel FIR digital filter implementations
10. Algorithms for low power and high speed FIR filter realization using differential coefficients
11. Decorrelating (DECOR) transformations for low-power adaptive filters
12. Algorithmic and architectural techniques for low power digital signal processing
13. Low power digital filters based on constrained least squares solution
14. Power efficient FIR folding transformation for wireline digital communications
15. Synthesis of low power folded programmable coefficient FIR digital filters
16. Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination
17. Synthesis of multiplier-less FIR filters with minimum number of additions
18. Subexpression sharing in filters using canonic signed digit multipliers
19. A new algorithm for the elimination of common subexpressions in hardware implementation of digital filters by using genetic programming
20. A new algorithm for elimination of common subexpressions
21. Coefficient transformations for area-efficient implementation of multiplier-less FIR filters
22. A novel design methodology for high performance and low power digital filters
23. Minimizing quantization effects using the TMS320 digital signal processor family