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Volumn E79-A, Issue 8, 1996, Pages 1120-1128

Fast FIR digital filter structures using minimal number of adders and its application to filter design

Author keywords

CSD expression; FIR digital filter; MILP

Indexed keywords

ADDERS; ALGORITHMS; CODES (SYMBOLS); COMPUTER SIMULATION; FREQUENCY RESPONSE; INTEGER PROGRAMMING; LOGIC CIRCUITS;

EID: 0030219197     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (23)

References (10)
  • 1
    • 0026185636 scopus 로고
    • FIRGEN: A computer-aided design system for high performance FIR filter integrated circuits
    • July
    • R. Jain, P.T. Yang, and T. Yoshino, "FIRGEN: A computer-aided design system for high performance FIR filter integrated circuits," IEEE Trans. Signal Process., vol.39, no.7, pp.1655-1668, July 1991.
    • (1991) IEEE Trans. Signal Process , vol.39 , Issue.7 , pp. 1655-1668
    • Jain, R.1    Yang, P.T.2    Yoshino, T.3
  • 2
    • 0029346550 scopus 로고
    • Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters
    • July
    • D. Li, "Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters," IEEE Trans. Circuits & Syst., vol.42, no.7, pp.453-460, July 1995.
    • (1995) IEEE Trans. Circuits & Syst. , vol.42 , Issue.7 , pp. 453-460
    • Li, D.1
  • 3
    • 0026293034 scopus 로고
    • Optimization of canonic signed digit multipliers for filter design
    • June
    • R. Hartley, "Optimization of canonic signed digit multipliers for filter design," Proc. IEEE Int. Symp. Circuits & Syst., pp.1992-1995, June 1991.
    • (1991) Proc. IEEE Int. Symp. Circuits & Syst. , pp. 1992-1995
    • Hartley, R.1
  • 4
    • 0029374075 scopus 로고
    • Use of minimum-adder multiplier blocks in FIR digital filters
    • Sept.
    • A.G. Dempster and M.D. Macleod, "Use of minimum-adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits & Syst., vol.42, no.9, pp.569-577, Sept. 1995.
    • (1995) IEEE Trans. Circuits & Syst. , vol.42 , Issue.9 , pp. 569-577
    • Dempster, A.G.1    Macleod, M.D.2
  • 5
    • 0024699067 scopus 로고
    • An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients
    • July
    • H. Samueli, "An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients," IEEE Trans. Circuits & Syst., vol.36, no.7, pp.1044-1047, July 1989.
    • (1989) IEEE Trans. Circuits & Syst. , vol.36 , Issue.7 , pp. 1044-1047
    • Samueli, H.1
  • 6
    • 0025592978 scopus 로고
    • Design of discrete-coefficient-value linear phase FIR filters with optimum normalized peak ripple magnitude
    • Dec.
    • Y.C. Lim, "Design of discrete-coefficient-value linear phase FIR filters with optimum normalized peak ripple magnitude," IEEE Trans. Circuits & Syst., vol.37, no.12, pp.1480-1486, Dec. 1990.
    • (1990) IEEE Trans. Circuits & Syst. , vol.37 , Issue.12 , pp. 1480-1486
    • Lim, Y.C.1
  • 7
    • 0026820480 scopus 로고
    • Applications of simulated annealing for the design of special digital filters
    • Feb.
    • N. Benvenuto, M. Marchesi, and A. Uncini, "Applications of simulated annealing for the design of special digital filters," IEEE Trans. Signal Process., vol.40, no.2, pp.323-332, Feb. 1992.
    • (1992) IEEE Trans. Signal Process. , vol.40 , Issue.2 , pp. 323-332
    • Benvenuto, N.1    Marchesi, M.2    Uncini, A.3
  • 9
    • 0030103513 scopus 로고    scopus 로고
    • Design of FIR digital filters using estimates of error function over CSD coefficient space
    • March
    • M. Yagyu, A. Nishihara, and N. Fujii, "Design of FIR digital filters using estimates of error function over CSD coefficient space," IEICE Trans. Fundamentals, vol.E79-A, no.3, pp.283-290, March 1996.
    • (1996) IEICE Trans. Fundamentals , vol.E79-A , Issue.3 , pp. 283-290
    • Yagyu, M.1    Nishihara, A.2    Fujii, N.3
  • 10
    • 0026172031 scopus 로고
    • Decomposition of binary integers into signed power-of-two terms
    • June
    • Y.C. Lim, J.B. Evans, and B. Liu, "Decomposition of binary integers into signed power-of-two terms," IEEE Trans. Circuits & Syst., vol.38, no.6, pp.667-672, June 1991.
    • (1991) IEEE Trans. Circuits & Syst. , vol.38 , Issue.6 , pp. 667-672
    • Lim, Y.C.1    Evans, J.B.2    Liu, B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.