Fanout fault analysis for digital logic circuits

Proceedings of the Asian Test Symposium

Volumn , Issue , 1995, Pages 33-39

  Chen, Jwu E ^a   Lee, Chung Len ^a   Shen, Wen Zen ^a   Chen, Beyin ^a  

^a CHUNG HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ERROR DETECTION; FAILURE ANALYSIS; SEQUENTIAL CIRCUITS;

DIGITAL LOGIC CIRCUITS; FANOUT FAULT ANALYSIS; FAULT COLLAPSING METHOD; FAULT SIMULATION; PATH CHECK CRITERIA; PATH INVERSION PARITY; TEST GENERATION;

LOGIC CIRCUITS;

EID: 0029487641     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ats.1995.485313     Document Type: Conference Paper

References (10)