TA-PSV-timing analysis for partially specified vectors

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 1, 2002, Pages 73-88

  Chen, Liang Chi ^a   Gupta, Sandeep K ^a   Breuer, Melvin A ^a  

^a University of Southern California   (United States)

Author keywords

Crosstalk test generation (ATPG); Delay model; Static timing analysis (STA); Timing analysis for partially specified vectors (TA PSV)

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; MATHEMATICAL MODELS; NUMERICAL ANALYSIS;

CROSSTALK TEST GENERATION; PARTIALLY SPECIFIED VECTORS; STATIC TIMING ANALYSIS; TIMING ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0036471605     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1013732107714     Document Type: Article

References (18)

1. Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time
2. A modeling technique for CMOS gates
3. Incremental timing analysis-intuition and implementation
4. A new framework for static timing analysis, incremental timing analysis, and timing simulation
5. A new gate delay model for simultaneous switching and its applications
6. Test generation for crosstalk noise in VLSI circuits
7. Analytic models for crosstalk delay and pulse analysis under non-ideal inputs
8. Test generation in VLSI circuits for crosstalk noise
9. Test generation for crosstalk-induced delay in integrated circuits
10. An implicit enumeration algorithm to generate tests for combinational logic circuits
11. Timing verification and timing analysis program
12. An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation
13. Inverter models of CMOS gates for supply current and delay evaluation
14. SPICE2, a computer program to simulate semiconductor circuits
15. ILLIADS: A fast timing and reliability simulator for digital MOS circuits
16. Piecewise approximate circuit simulation