SCOPUS 정보 검색 플랫폼

Volumn , Issue , 2002, Pages 648-656

Re-using DFT logic for functional and silicon debugging test

(5) Gu, Xinli a Wang, Weili a Li, Kevin a Kim, Heon a Chung, Sung S a

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; FLIP FLOP CIRCUITS; INTERCONNECTION NETWORKS; LOGIC DESIGN; RANDOM ACCESS STORAGE; SEQUENTIAL CIRCUITS; SILICON;

CHIP MANUFACTURING TEST; DESIGN FOR TESTABILITY LOGIC; SILICON DEBUGGING TEST;

DESIGN FOR TESTABILITY;

EID: 0036446825 PISSN: 10893539 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (19)

References (9)

1
- 0003500979
- Kluwer Academic Publishers
- K. P. Parker, The Boundary-Scan Handbook, Second Edition, Kluwer Academic Publishers, 2000.
- (2000) The Boundary-Scan Handbook, Second Edition
- Parker, K.P.¹

2
- 0035684101
- An effort-minimized logic BIST implementation method
- X. Gu, S. S. Chung, F. Tsang, J.A. Tofte and H. Rahmanian, An Effort-Minimized Logic BIST Implementation Method, Proc. of International Test Conference, pp. 1002-1010, 2001.
- (2001) Proc. of International Test Conference , pp. 1002-1010
- Gu, X.¹ Chung, S.S.² Tsang, F.³ Tofte, J.A.⁴ Rahmanian, H.⁵

3
- 0033309980
- Logic BIST for large industrial designs: Real issues and case studies
- G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J Rajski, "Logic BIST for Large Industrial Designs: Real Issues and Case Studies", Proc. of International Test Conference, pp. 358-367, 1999.
- (1999) Proc. of International Test Conference , pp. 358-367
- Hetherington, G.¹ Fryars, T.² Tamarapalli, N.³ Kassab, M.⁴ Hassan, A.⁵ Rajski, J.⁶

4
- 0035687658
- OPMISR: The foundation for compressed ATPG vectors
- C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, B. Koenemann, "OPMISR: The Foundation for Compressed ATPG Vectors", Proc. of International Test Conference, pp. 748-757, 2001.
- (2001) Proc. of International Test Conference , pp. 748-757
- Barnhart, C.¹ Brunkhorst, V.² Distler, F.³ Farnsworth, O.⁴ Keller, B.⁵ Koenemann, B.⁶

5
- 0035680666
- AC-JTAG: Empowering JTAG beyond testing DC nets
- S. Baeg, S. Chung, "AC-JTAG: Empowering JTAG Beyond Testing DC Nets", Proc. of International Test Conference, pp. 30-37, 2001.
- (2001) Proc. of International Test Conference , pp. 30-37
- Baeg, S.¹ Chung, S.²

6
- 0011874019
- AC boundary-scan specification for MSA
- Cisco Systems, Inc. [Cisco2001]
- S. Baeg, S. Chung, "AC Boundary-Scan Specification for MSA" Cisco Systems, Inc. [Cisco2001].
- Baeg, S.¹ Chung, S.²

7
- 0003731578
- Design for at-speed test, diagnosis and measurement
- Kluwer Academic Publishers
- B. Nadeau-Dostie, "Design for At-Speed Test, Diagnosis And Measurement", Kluwer Academic Publishers, 2000.
- (2000)
- Nadeau-Dostie, B.¹

8
- 0035684208
- A building block BIST methodology for SOC design: A case study
- P. Gallagher, V. Chickerman, S. Gregpr, "A Building Block BIST Methodology for SOC Design: A Case Study", Proc. of International Test Conference, pp.111-120, 2001.
- (2001) Proc. of International Test Conference , pp. 111-120
- Gallagher, P.¹ Chickerman, V.² Gregpr, S.³

9
- 0035687174
- Debug methodology for the McKinley Processor
- D. Josephson, S. Poehlman, and V. Govan, "Debug Methodology for the McKinley Processor", Proc. International Test Conference, pp.451-460, 2001.
- (2001) Proc. International Test Conference , pp. 451-460
- Josephson, D.¹ Poehlman, S.² Govan, V.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.