An Effort-Minimized logic BIST implementation method

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 1002-1010

  Gu, Xinli ^a   Chung, Sung Soo ^a   Tsang, Frank ^a   Tofte, Jan A ^b   Rahmanian, Hamid ^b  

^a CISCO SYSTEMS   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; FLIP FLOP CIRCUITS; LOGIC DESIGN; PROGRAM DEBUGGING; SHIFT REGISTERS;

STATIC TIMING ANALYSIS;

BUILT-IN SELF TEST;

EID: 0035684101     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966725     Document Type: Article

References (5)

1. Logic BIST for large industrial designs: Real issues and case studies
2. Low overhead test point insertion for scan-based BIST
3. Timing driven test point insertion for full-scan and partial-scan BIST