-
1
-
-
0031152477
-
Logic emulation with virtual wires
-
June
-
J. Babb, R. Tessier, M. Dahl, S. Hanono, D. Hoki, and A. Agarwal. Logic Emulation with Virtual Wires. IEEE Transactions on Computer Aided Design, 16(6):609-626, June 1997.
-
(1997)
IEEE Transactions on Computer Aided Design
, vol.16
, Issue.6
, pp. 609-626
-
-
Babb, J.1
Tessier, R.2
Dahl, M.3
Hanono, S.4
Hoki, D.5
Agarwal, A.6
-
2
-
-
0012135452
-
Maps: A compiler-managed memory system for raw machines
-
Technical report, M.I.T. LCS-TM-583, July
-
Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal. Maps: A Compiler-Managed Memory System for Raw Machines. Technical report, M.I.T. LCS-TM-583, July 1998. Also http://www.cag.lcs.mit.edu/raw/.
-
(1998)
-
-
Barua, R.1
Lee, W.2
Amarasinghe, S.3
Agarwal, A.4
-
5
-
-
0030264269
-
An integrated compile-time/run-time software distributed shared memory system
-
Cambridge, Massachusetts, October 1-5
-
Sandhya Dwarkadas, Alan L. Cox, and Willy Zwaenepoel. An integrated compile-time/run-time software distributed shared memory system. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 186-197, Cambridge, Massachusetts, October 1-5, 1996.
-
(1996)
Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 186-197
-
-
Dwarkadas, S.1
Cox, A.L.2
Zwaenepoel, W.3
-
6
-
-
0025807368
-
Building and using a highly parallel programmable logic array
-
January
-
Maya Gokhale, William Holmes, Andrew Kopser, Sara Lucas, Ronald Minnich, Douglas Sweeney, and Daniel Lopresti. Building and using a highly parallel programmable logic array. Computer, 24(1), January 1991.
-
(1991)
Computer
, vol.24
, Issue.1
-
-
Gokhale, M.1
Holmes, W.2
Kopser, A.3
Lucas, S.4
Minnich, R.5
Sweeney, D.6
Lopresti, D.7
-
8
-
-
0030380793
-
Maximizing multiprocessor performance with the suif compiler
-
December
-
M. W. Hall, J. M. Anderson, S. P. Amarasinghe, B. R. Murphy, S.-W. Liao, E. Bugnion, and M. S. Lam. Maximizing multiprocessor performance with the suif compiler. COMPUTER, 29(12):84-89, December 1996.
-
(1996)
COMPUTER
, vol.29
, Issue.12
, pp. 84-89
-
-
Hall, M.W.1
Anderson, J.M.2
Amarasinghe, S.P.3
Murphy, B.R.4
Liao, S.-W.5
Bugnion, E.6
Lam, M.S.7
-
10
-
-
0031238171
-
Scalable processors in the billion transistors era: IRAM
-
September
-
Christoforos E. Kozyrakis, Stylianos Perissakis, David Patterson, Thomas Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Randi Thomas, Noah Treuhaft, and Katherine Yelick. Scalable processors in the billion transistors era: IRAM. IEEE Computer, pages 75-78, September 1997.
-
(1997)
IEEE Computer
, pp. 75-78
-
-
Kozyrakis, C.E.1
Perissakis, S.2
Patterson, D.3
Anderson, T.4
Asanovic, K.5
Cardwell, N.6
Fromm, R.7
Golbus, J.8
Gribstad, B.9
Keeton, K.10
Thomas, R.11
Treuhaft, N.12
Yelick, K.13
-
11
-
-
0031599788
-
Space-time scheduling of instruction-level parallelism on a raw machine
-
San Jose, CA, October
-
Walter Lee, Rajeev Barua, Matthew Frank, Devabhatuni Srikrishna, Jonathan Babb, Vivek Sarkar, and Saman Amarasinghe. Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. In Proceedings of the Eighth ACM Conference on Architectural Support for Programming Languages and Operating Systems, pages 46-57, San Jose, CA, October 1998.
-
(1998)
Proceedings of the Eighth ACM Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 46-57
-
-
Lee, W.1
Barua, R.2
Frank, M.3
Srikrishna, D.4
Babb, J.5
Sarkar, V.6
Amarasinghe, S.7
-
12
-
-
0012179438
-
-
personal communications. Stanford University Smart Memories Project
-
Mark Horowitz, personal communications. Stanford University Smart Memories Project. http://velox.stanford.edu/smart_memories.
-
-
-
Horowitz, M.1
-
13
-
-
85013607448
-
NAPA C: Compiling for a hybrid RISC/FPGA Architecture
-
Sarnoff Corporation.; Napa Valley, California, April
-
Maya B. Gokhale, Janice M. Stone, Matthew Frank, Sarnoff Corporation. NAPA C: Compiling for a Hybrid RISC/FPGA Architecture. In FCCM98 Napa Valley, California, April 1998.
-
(1998)
FCCM98
-
-
Gokhale, M.B.1
Stone, J.M.2
Frank, M.3
-
14
-
-
33746318271
-
Data-parallel C on a reconfigurable logic array
-
September
-
Maya Gokhale and Brian Schott. Data-Parallel C on a Reconfigurable Logic Array. Journal of Supercomputing, September 1995.
-
(1995)
Journal of Supercomputing
-
-
Gokhale, M.1
Schott, B.2
-
15
-
-
0012133220
-
Span: A shape and pointer analysis package
-
Technical report, M.I.T. LCS-TM-581, June
-
Radu Rugina and Martin Rinard. Span: A shape and pointer analysis package. Technical report, M.I.T. LCS-TM-581, June 1998.
-
(1998)
-
-
Rugina, R.1
Rinard, M.2
-
16
-
-
0030263178
-
Shasta: A low overhead, software-only approach for supporting fine-grain shared memory
-
Cambridge, Massachusetts, October 1-5
-
Daniel J. Scales, Kourosh Gharachorloo, and Chandramohan A. Thekkath. Shasta: A low overhead, software-only approach for supporting fine-grain shared memory. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 174-185, Cambridge, Massachusetts, October 1-5, 1996.
-
(1996)
Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 174-185
-
-
Scales, D.J.1
Gharachorloo, K.2
Thekkath, C.A.3
-
17
-
-
84957917534
-
PRISM II Compiler and Architecture
-
Napa, CA, April; IEEE
-
A. Smith, M. Wazlowski, L. Agarwal, T. Lee, E. Lam, P. Athans, H. Silverman, and S. Ghosh. PRISM II Compiler and Architecture. In Proceedings IEEE Workshop on FPGA-based Custom Computing Machines, pages 9-16, Napa, CA, April 1993. IEEE.
-
(1993)
Proceedings IEEE Workshop on FPGA-based Custom Computing Machines
, pp. 9-16
-
-
Smith, A.1
Wazlowski, M.2
Agarwal, L.3
Lee, T.4
Lam, E.5
Athans, P.6
Silverman, H.7
Ghosh, S.8
-
19
-
-
0030104367
-
Programmable active memories: Reconfigurable systems come of age
-
March
-
J. E. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. H. Touati, and P. Boucard. Programmable Active Memories: Reconfigurable Systems Come of Age. IEEE Transactions on VLSI Systems, 4(1), March 1996.
-
(1996)
IEEE Transactions on VLSI Systems
, vol.4
, Issue.1
-
-
Vuillemin, J.E.1
Bertin, P.2
Roncin, D.3
Shand, M.4
Touati, H.H.5
Boucard, P.6
-
20
-
-
0031236158
-
Baring it all to software: Raw machines
-
September; Also available as MIT-LCS-TR-709
-
Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal. Baring It All to Software: Raw Machines. IEEE Computer, 30(9):86-93, September 1997. Also available as MIT-LCS-TR-709.
-
(1997)
IEEE Computer
, vol.30
, Issue.9
, pp. 86-93
-
-
Waingold, E.1
Taylor, M.2
Srikrishna, D.3
Sarkar, V.4
Lee, W.5
Lee, V.6
Kim, J.7
Frank, M.8
Finch, P.9
Barua, R.10
Babb, J.11
Amarasinghe, S.12
Agarwal, A.13
-
21
-
-
0003770595
-
Compilation and pipeline synthesis for reconfigurable architectures - High performance by configware
-
M. Weinhardt. Compilation and Pipeline Synthesis for Reconfigurable Architectures - High Performance by Configware. In Reconfigurable Architecture Workshop, 1997.
-
Reconfigurable Architecture Workshop, 1997
-
-
Weinhardt, M.1
|