High-speed pipelined A/D converter using time-shifted CDS technique

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Li, Jipeng ^a   Moon, Un Ku ^a  

^a 1148 Kelley Engineering Center Corvallis   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; DIGITAL COMMUNICATION SYSTEMS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POTENTIAL; OPERATIONAL AMPLIFIERS; PIPELINE PROCESSING SYSTEMS;

CAPACITOR MISMATCH; FINITE OPAMP GAIN; TIME SHIFTED CORRELATED DOUBLE SAMPLING; WAVEFORM ACQUISITION SYSTEM;

ANALOG TO DIGITAL CONVERSION;

EID: 0036296915     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. An 8-bit 80-MSample/s pipelined analog-to-digital converter with background calibration
2. Area-efficient self-calibration technique for pipelined algorithmic A/D converters
3. A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC
4. A continuously calibrated 12-b, 10-Ms/s, 3.3-V A/D converter
5. Correction of operational amplifier gain error in pipelined A/D converters
6. Switched-capacitor circuits with reduced sensitivity to amplifier gain