High-speed add-compare-select units using locally self-resetting CMOS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages 889-892

  Jung, Gunok ^a   Kong, Jun Jin ^a   Sobelman, Gerald E ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC GATES;

ADD-COMPARE-SELECT UNIT; BRANCH METRIC CALCULATOR; KOGGE-STONE ARCHITECTURE; SELF-RESETTING CMOS; VITERBI DECODER;

DECODING;

EID: 0036295899     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1009984     Document Type: Article

References (10)

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9. Optimal clocking and enhanced testability for high-performance self-resetting domino pipelines
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