Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 8, 1999, Pages 1108-1117

  Hwang, Wei ^a   Gristede, George Diedrich ^a   Sanda, Pia ^a   Wang, Shao Y ^b   Heidel, David F ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Och Spine at New York Presbyterian Hospitals   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MICROPROCESSOR CHIPS;

CMOS DIGITAL INTEGRATED CIRCUITS; DYNAMIC LOGIC CIRCUITS; HIGH SPEED INTEGRATED CIRCUITS; SELF RESETTING CMOS;

ADDERS;

EID: 0033169549     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.777109     Document Type: Article

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