Integrated 64-state parallel analog Viterbi decoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2000, Pages

  He, Kai ^a   Cauwenberghs, Gert ^a  

^a JOHNS HOPKINS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; SIGNAL TO NOISE RATIO; VLSI CIRCUITS;

VITERBI DECODERS;

DECODING;

EID: 0033697543     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.858863     Document Type: Conference Paper

References (5)