Area-efficient analog VLSI architecture for state-parallel viterbi decoding

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1999, Pages

  He, Kai ^a   Cauwenberghs, Gert ^a  

^a JOHNS HOPKINS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; DECODING; DIGITAL COMMUNICATION SYSTEMS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT TESTING; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS;

ADD COMPARE SELECT MODULE; SWITCHED CAPACITOR; VITERBI DECODING;

VLSI CIRCUITS;

EID: 0001635258     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)