A high-speed FFT processor for OFDM systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages 281-284

  Son, Byung S ^a   Jo, Byung G ^a   Sunwoo, Myung H ^a   Kim, Yong Serk ^b  

^a Ajou University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; FAST FOURIER TRANSFORMS; LOGIC DESIGN; LOGIC GATES; RANDOM ACCESS STORAGE; STORAGE ALLOCATION (COMPUTER);

DISCRETE MULTITONE; HIGH SPEED PROCESSOR; IN PLACE MEMORY ADDRESSING; LOGIC SYNTHESIS; RADIX ALGORITHM; SINGLE MEMORY ARCHITECTURE; VERILOG HARDWARE DESCRIPTION LANGUAGE;

ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;

EID: 0036294832     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1010215     Document Type: Article

References (14)

1. A novel DHT-based FFT/IFFT processor for ADSL transceivers
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3. A pipelined shared-memory architecture for FFT processor
4. A low power, high performance, 1024-point FFT processor
5. Area-efficient architecture for fast Fourier transform
6. Design of an efficient FFT processor for DAB systems
7. Design and implementation of an FFT processor for VDSL
8. Conflict free memory addressing for dedicated FFT hardware
9. An OFDM transmission scheme using cyclic suffix
10. Design and implementation of a 1024-point pipeline FFT processor
11. VLSI for OFDM