Area-efficient architecture for Fast Fourier Transform

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 46, Issue 2, 1999, Pages 187-193

  Hidalgo, Jose Antonio ^a   Lopez, Juan ^a   Argüello, Francisco ^a   Zapata, Emilio L ^a  

^a UNIVERSITY OF MÁLAGA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER NETWORKS; DATA FLOW ANALYSIS; DIGITAL ARITHMETIC; PARALLEL PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER);

AREA EFFICIENT PARALLEL ARCHITECTURE; CONSTANT GEOMETRY FAST FOURIER TRANSFORM; SPECIFIC PURPOSE PROCESSOR;

FAST FOURIER TRANSFORMS;

EID: 0033075873     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.752951     Document Type: Article

References (12)

1. B. Holland and J. MatherMonolithic frequency domain processing with 450 MFLOPS throughput," Electron. Eng., pp. 29-36, Aug. 1989.
2. E. Bidet, D. Castelain, C. Joanblanq, and P. SennA fast singlechip implementation of 8192 complex point FFT," IEEE J. Solid State Circuits, vol. 30, Mar. 1995.
3. H. Miyanaga and H. YamauchiA 400 MFLOPS processor VLSI architecture," 1EICE Trans., vol. L-74, no. 11, pp. 3845-3851, Nov. 1991.
4. J. A. Hidalgo-Lopez, J. C. Tejero, J. Fernandez, E. Herruzo, and A. GagoNew architecture for RFFT calculation," Electron. Lett., vol. 30, no. 22, Oct. 1994.
5. E. L. Zapata and F. ArgüelloApplication-specific architecture for fast transforms based on the succesive doubling method," IEEE Trans. Signal Processing, vol. 41, pp. 1476-1481, Oct. 1993.
6. G. MielConstant geometry fast fourier transforms on array processors," IEEE Trans. Computers, vol. 42, pp. 371-375, Mar. 1993.
7. S. F. Gorman and J. M. WillsPartial column FFT pipelines," IEEE Trans. Circuits Syst., vol. 42, June 1995.
8. F. Argüello, J. D. Bruguera, R. Doallo, and E. L. ZapataParallel architecture for fast transforms with trigonometric kernel," IEEE Trans. Parallel Distributed Syst., vol. 5, pp. 1091-1099, Mar. 1994.
9. J. Lopez and E. L. ZapataUnified architecture for divide and conquer based tridiagonal systems solvers," IEEE Trans. Computers, vol. 43, pp. 1413-1421, Dec. 1994.
10. M. C. PeaseAn adaptation of the fast fourier transform for parallel processing," J. ACM, vol. 15, pp. 252-264, 1968.
11. C. B. Shung, H. D. Lin, R. Cypher, P. H. Siegel, and H. K. ThaparArea-efficient architectures for the Viterbi algorithm-Part I: Theory," IEEE Trans. Commun., vol. 41, pp. 636-643, Apr. 1993.
12. C. D. ThompsonFourier transforms in VLSI," IEEE Trans. Computers, vol. C-32, pp. 1047-1057, Nov. 1983.