Low power clock generator based on an area-reduced interleaved synchronous mirror delay scheme

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages

  Sung, Kihyuk ^a   Yang, Byung Do ^a   Kim, Lee Sup ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC INVERTERS; MULTIPLEXING EQUIPMENT; PULSE GENERATORS;

BACKWARD DELAY ARRAY; CLOCK GENERATOR; FORWARD DELAY ARRAY; SYNCHRONOUS MIRROR DELAY;

TIMING CIRCUITS;

EID: 0036292981     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. A PLL clock generator with 5 to 100MHz of lock range for microprocessors
2. An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors
3. A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay
4. A 10ps jitter 2 clock cycle lock time CMOS digital clock generator based on an interleaved synchronous mirror delay scheme
5. A direct-skew-detect synchronous mirror delay for application-specific integrated circuits
6. An analog synchronous mirror delay for high-speed DRAM application
7. Wide range single-way-pumping synchronous mirror delay
8. ASMD with duty cycle correction scheme for high-speed DRAM