Wide range single-way-pumping synchronous mirror delay

Electronics Letters

Volumn 36, Issue 11, 2000, Pages 939-940

  Chae, Jeong Seok ^a   Kim, Daejeong ^a   Kim, Dong Myeong ^a  

^a Kookmin University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0000937219     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000711     Document Type: Article

References (4)

1. LEE, T., DONNELLY, K., HO, J., ZERBE, J., JOHNSON, M., and ISHIKAWA, T.: 'A 2.5V CMOS delay-locked loop for an 18Mbit, 500Mb/s DRAM', IEEE J. Solid-State Circuits, 1994, SC-29, (12), pp. 1491-1496
2. TAKAI, Y., FUJITA, M., NAGATA, K., ISA, S., NAKAZAWA, S., HIROBE, A., OHKUBO, H., SAKAO, M., HORIBA, S., FUKASE, T., TAKAISHI, Y., MATSUO, M., KOMURO, M., UCHIDA, T., SAKOH, T., SAINO, K., UCHIYAMA, S., TAKADA, Y., SEKINE, J., NAKANISHI, N., OIKAWA, T., IGETA, M., TANABE, H., MIYAMOTO, H., HASHIMOTO, T., YAMAGUCHI, H., KOYAMA, K., KOBAYASHI, Y., and OKUDA. T.: 'A 250 Mb/s pin 1Gb double data rate SDRAM with bidirectional delay and an inter-bank shares redundancy scheme'. ISSCC Dig. Tech. Papers, 1999, pp. 418-419
3. SAEKI, T., NAKAOKA, Y., FUJITA, M., TANAKA, A., NAGATA, K., SAKAKIBARA, K., MATANO, T., HOSINO, Y., MIYANO, K., ISA. S., NAKAZAWA, S., KAKEHASHI, E., DRYNAN, J., KOMURO, M., FUKASE, T., IWASAKI, H., TAKENAKA, M., SEKINE, J., IGETA, M., NAKANISHI, N., ITANI, T., YOSHIDA, K., YOSHINO, H., HASHIMOTO, S., YOSHII, T., ICHINOSE, M., IMURA, T., UZIE, M., KIKUCHI, S., KOYAMA, K., FUKUZO, Y., and OKUBO, T.: 'A 2.5ns clock access, 25O MHz, 256Mb SDRAM with synchronous mirror delay', IEEE J. Solid State Circuits, 1996, SC-31, pp. 1656-1668
4. SHIM, D., LEE, D., JUNG, S., KIM, C., and KIM, W.: 'An analog synchronous mirror delay for high-speed DRAM application', IEEE J. Solid-State Circuits, 1999, SC-34, (4), pp. 484-493